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公开(公告)号：US20210182178A1
公开(公告)日：2021-06-17
申请号：US16712593
申请日：2019-12-12
Applicant: SanDisk Technologies LLC
Inventor： Masakazu EHAMA , Hiroyuki Mizukoshi , Yan Li
Abstract: A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.
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Patent Agency Ranking
12.发明公开公开(公告)号：US20230326530A1
公开(公告)日：2023-10-12
申请号：US17715647
申请日：2022-04-07
Applicant: SanDisk Technologies LLC
Inventor： Chin-Yi Chen , Muhammad Masuduzzaman , Kou Tei , Deepanshu Dutta , Hiroyuki Mizukoshi , Jiahui Yuan , Xiang Yang
CPC classification number: G11C16/26 , G11C16/08 , G11C16/3459 , G11C16/0483 , G11C16/10 , G11C11/5621
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.
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公开(公告)号：US11561883B2
公开(公告)日：2023-01-24
申请号：US16712593
申请日：2019-12-12
Applicant: SanDisk Technologies LLC
Inventor： Masakazu Ehama , Hiroyuki Mizukoshi , Yan Li
Abstract: A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.
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公开(公告)号：US11334294B2
公开(公告)日：2022-05-17
申请号：US16909467
申请日：2020-06-23
Applicant: SanDisk Technologies LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
IPC: G06F3/06 , G06F9/30 , G06F9/38 , G11C11/00 , G11C5/06 , G11C11/4072 , G06F8/65 , G11C29/16 , G11C5/14 , G11C16/28 , G11C11/56 , G11C29/46 , G11C16/34 , G11C16/24 , G11C16/10 , G11C16/08
Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
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公开(公告)号：US10908817B2
公开(公告)日：2021-02-02
申请号：US16003515
申请日：2018-06-08
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Tai-Yuan Tseng , Hiroyuki Mizukoshi , Chi-Lin Hsu , Yan Li
IPC: G06F3/06 , G11C16/10 , G11C16/34 , G11C16/26 , G11C11/56 , G11C5/06 , G11C16/08 , G11C8/12 , G11C7/10 , G11C8/08 , G11C16/04
Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.
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公开(公告)号：US10824376B2
公开(公告)日：2020-11-03
申请号：US15994116
申请日：2018-05-31
Applicant: SanDisk Technologies LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
IPC: G06F3/06 , G06F9/30 , G06F9/38 , G11C11/00 , G11C5/06 , G11C11/4072 , G06F8/65 , G11C29/16 , G11C5/14 , G11C16/28 , G11C11/56 , G11C29/46 , G11C16/34 , G11C16/24 , G11C16/10 , G11C16/08
Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
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