中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.018 seconds)

    Non-volatile memory with fast data cache transfer scheme
    11.
    发明授权
    Non-volatile memory with fast data cache transfer scheme 有权

    公开(公告)号：US10811082B1

    公开(公告)日：2020-10-20

    申请号：US16450058

    申请日：2019-06-24

    Applicant: SanDisk Technologies LLC

    Inventor： YenLung Li ,  Hua-Ling Cynthia Hsu ,  Chen Chen ,  Min Peng

    IPC: G11C7/18 ,  G11C11/409 ,  G06F3/06

    Abstract: In a non-volatile memory circuit, read and write performance is improved by increasing the transfer rate of data through the cache buffer during read and write operations. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, pairs of data words are stored interleaved on the bit lines of a pair of columns. Data is transferred in and out of the read and write circuit on an internal bus structure, where part of the transfer of one word stored on a pair of columns can overlap with part of the transfer of another word, accelerating transfer times for both read and write.

    COMMAND AND ADDRESS SEQUENCING IN PARALLEL WITH DATA OPERATIONS
    14.
    发明公开
    COMMAND AND ADDRESS SEQUENCING IN PARALLEL WITH DATA OPERATIONS 审中-公开

    公开(公告)号：US20230350606A1

    公开(公告)日：2023-11-02

    申请号：US17732260

    申请日：2022-04-28

    Applicant: SanDisk Technologies LLC

    Inventor： Hua-Ling Cynthia Hsu ,  Fanglin Zhang

    IPC: G06F3/06 ,  G06F13/16

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F13/1668

    Abstract: A command/address sequence associated with a read/write operation for a memory device that utilizes an existing test data bus in a novel way that obviates the need to utilize an I/O bus for the command/address sequence. As such, the command/address sequence can be performed in parallel with the read/write operations, thereby removing a performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence detects a first enable signal and a data signal on the test data bus and decodes the data signal to obtain at least one of a command latch enable signal and address latch enable signal and at least one of a command code and an address code.

    NON-VOLATILE STORAGE SYSTEM WITH POWER ON READ TIMING REDUCTION
    15.
    发明公开
    NON-VOLATILE STORAGE SYSTEM WITH POWER ON READ TIMING REDUCTION 审中-公开

    公开(公告)号：US20230260589A1

    公开(公告)日：2023-08-17

    申请号：US17672904

    申请日：2022-02-16

    Applicant: SanDisk Technologies LLC

    Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

    IPC: G11C29/50

    CPC classification number: G11C29/50004 ,  G11C2029/5004

    Abstract: Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.

    ON-THE-FLY MULTIPLEXING SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES
    16.
    发明申请
    ON-THE-FLY MULTIPLEXING SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES 有权

    公开(公告)号：US20230095127A1

    公开(公告)日：2023-03-30

    申请号：US17731971

    申请日：2022-04-28

    Applicant: SanDisk Technologies LLC

    Inventor： YenLung Li ,  Siddarth Naga Murty Bassa ,  Chen Chen ,  Hua-Ling Cynthia Hsu

    IPC: G06F3/06

    Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

    VERTICAL COMPRESSION SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES WITH DATA LATCH GROUPS
    17.
    发明申请
    VERTICAL COMPRESSION SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES WITH DATA LATCH GROUPS 有权

    公开(公告)号：US20230085405A1

    公开(公告)日：2023-03-16

    申请号：US17731961

    申请日：2022-04-28

    Applicant: SanDisk Technologies LLC

    Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

    DIGITAL TEMPERATURE COMPENSATION FILTERING
    18.
    发明申请
    DIGITAL TEMPERATURE COMPENSATION FILTERING 有权

    公开(公告)号：US20220406383A1

    公开(公告)日：2022-12-22

    申请号：US17352095

    申请日：2021-06-18

    Applicant: SanDisk Technologies LLC

    Inventor： Henry Chin ,  Hua-Ling Cynthia Hsu ,  Wei Zhao ,  Fanglin Zhang

    IPC: G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G06F1/20

    Abstract: Techniques disclosed herein cope with temperature effects in non-volatile memory systems. A control circuit is configured to sense a current temperature of the memory system and read, verify, program, and erase data in non-volatile memory cells by modifying one or more read/verify/program/erase parameters based on a temperature compensation value. The control circuit is further configured to read, verify, program, and erase data by accessing a historical temperature value stored in the memory system, the historical temperature value comprising a temperature at which a previous read, verify, program or erase occurred and measuring a current temperature value. The control circuit determines the temperature compensation value by applying a smoothing function. The smoothing function determines the temperature compensation value by selecting either the historical temperature value or the current temperature value as the temperature compensation value based on a difference between the historical temperature value and the current temperature relative to a threshold, or calculating the temperature compensation value, different from the current temperature value or the historical temperature value, based a smoothing function which utilizes the current temperature value and the historical temperature value.

    NONVOLATILE MEMORY WITH ONGOING PROGRAM READ
    19.
    发明公开
    NONVOLATILE MEMORY WITH ONGOING PROGRAM READ 审中-公开

    公开(公告)号：US20240221803A1

    公开(公告)日：2024-07-04

    申请号：US18360273

    申请日：2023-07-27

    Applicant: SanDisk Technologies LLC

    Inventor： Hua-Ling Cynthia Hsu ,  Victor Avila ,  Henry Chin

    IPC: G11C7/10

    CPC classification number: G11C7/1096 ,  G11C7/106 ,  G11C7/1069

    Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to receive a read command directed to at least one logical page of data during a program operation to store the at least one logical page of data in a plurality of non-volatile memory cells. The control circuits are further configured to stop the program operation at an intermediate stage of programming, read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page and obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

Patent Agency Ranking