公开(公告)号：US10535412B2

公开(公告)日：2020-01-14

申请号：US15963647

申请日：2018-04-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Jianzhi Wu ,  Gerrit Jan Hemink

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/24 ,  G11C16/26 ,  G11C16/10

Abstract: A memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.

公开(公告)号：US20190378583A1

公开(公告)日：2019-12-12

申请号：US16205165

申请日：2018-11-29

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Xiang Yang ,  Zhenming Zhou ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

Abstract: An apparatus, system, and method are disclosed for identifying and selecting a subgroup of memory cells for use during a programming or erasing operation, in order to execute the programming or erasing operation in less time, while avoiding over and under programming errors. Memory devices disclosed herein may include a state change/programming circuit, a counting circuit, a determination circuit, an identification circuit, and/or a subgroup selection circuit, where each of these circuits are configured to perform operations related to the overall process of identifying and selecting the subgroup of memory cells for utilization during a programming operation.

公开(公告)号：US10026492B2

公开(公告)日：2018-07-17

申请号：US15640563

申请日：2017-07-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  Arash Hazeghi ,  Huai-Yuan Tseng ,  Cynthia Hsu ,  Navneeth Kankani

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/32

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

公开(公告)号：US20170178736A1

公开(公告)日：2017-06-22

申请号：US15385454

申请日：2016-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Xiaochang Miao ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5648

Abstract: Systems and methods for reducing residual electrons within a NAND string subsequent to performing a sensing operation using the NAND string or during the sensing operation. A middle-out programming sequence may be performed in which memory cell transistors in the middle of the NAND string are programmed and program verified prior to programming and verifying other memory cell transistors towards the drain-side end of the NAND string and/or the source-side end of the NAND string. In one example, for a NAND string with 32 memory cell transistors corresponding with word lines WL0 through WL31 from the source-side end of the NAND string to the drain-side end of the NAND string, the memory cell transistor corresponding with word line WL16 may be programmed and program verified prior to programming the memory cell transistors corresponding with word lines WL15 and WL17.

公开(公告)号：US11600343B2

公开(公告)日：2023-03-07

申请号：US17329390

申请日：2021-05-25

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Tomer Eliash ,  Huai-Yuan Tseng

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11565 ,  G11C11/56 ,  H01L25/065

Abstract: Technology is disclosed for an efficient read NAND memory cells while mitigating read disturb. In an aspect, a read sequence includes a read spike that removes residual electrons from the NAND channels, followed by reading multiple different groups of memory cells, followed by a channel clean operation. The read spike and channel clean mitigate read disturb. The read spike and channel clean each take a significant amount of time to perform. However, since multiple groups of memory cells are read between the read spike and channel clean this time is essentially spread over the reading of multiple groups, thereby improving the average time to read a single group of memory cells. In one aspect, reading the multiple different groups of memory cells includes reading one or more pages from each of the groups of memory cells. In one aspect, each group is in a different sub-block.

公开(公告)号：US11521686B2

公开(公告)日：2022-12-06

申请号：US17218498

申请日：2021-03-31

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Hua-Ling Hsu ,  Huai-Yuan Tseng ,  Fanglin Zhang

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and configured to retain a threshold voltage corresponding to one of a plurality of data states following a program operation. A control circuit is coupled to the word lines and the bit lines. The control circuit is configured to count a bit-scan quantity of the memory cells during a bit-scan of the program operation. The control circuit determines whether the bit-scan quantity of the plurality of memory cells is greater than at least one predetermined bit-scan threshold. In response to the bit-scan quantity of the memory cells being greater than the at least one predetermined bit-scan threshold, the control circuit is configured to adjust a word line ramp rate of a word line voltage applied to the word lines during the program operation.

公开(公告)号：US11385810B2

公开(公告)日：2022-07-12

申请号：US16916620

申请日：2020-06-30

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G06F3/06

Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

公开(公告)号：US11081180B2

公开(公告)日：2021-08-03

申请号：US16842112

申请日：2020-04-07

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C16/04 ,  G11C11/56 ,  G06F11/10 ,  G11C16/10 ,  G11C16/08 ,  G06F11/18 ,  H01L27/11556 ,  G11C16/34 ,  G11C16/24

Abstract: Techniques for fast programming and read operations for memory cells. A first set of bit lines is connected to a first set of NAND strings and is interleaved with a second set of bit lines connected to a second set of NAND strings. The first set of NAND strings can be programmed by driving a voltage on the first set of bit lines while floating a voltage on the second set of bit lines, to reduce an inter-bit line capacitance and provide a relatively high access speed and a relatively low storage density (e.g., bits per memory cell). The second set of NAND strings can be programmed by concurrently driving a voltage on the first and second sets of bit lines, to provide a relatively low access speed and a relatively high storage density.

公开(公告)号：US11062780B1

公开(公告)日：2021-07-13

申请号：US16729951

申请日：2019-12-30

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Jiahui Yuan ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.

公开(公告)号：US11024393B1

公开(公告)日：2021-06-01

申请号：US16738677

申请日：2020-01-09

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Ken Oowada ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

Abstract: An apparatus comprises a driver circuit, sense circuit, and die controller. The driver circuit supplies a pass voltage to a selected word line and unselected word lines, a sense voltage to an adjacent word line, and a bit line voltage to bit lines coupled to selected and unselected word lines. The sense circuit determines nonconducting and conducting memory cells on the adjacent word line. The die controller then directs the driver circuit to ramp the sense voltage on the adjacent word line to the pass voltage and ramp the pass voltage on the selected word line to ground. The die controller then directs the driver circuit to ramp the bit line voltage for bit lines coupled to nonconducting memory cells to a bit line compensation voltage and directs the sense circuit to read memory cells of the selected word line based on the bit line compensation voltage.