公开(公告)号：US11551781B1

公开(公告)日：2023-01-10

申请号：US17349321

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G11C16/26 ,  G11C29/00 ,  G11C29/02 ,  G11C16/34 ,  G11C16/10

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.

公开(公告)号：US20220254382A1

公开(公告)日：2022-08-11

申请号：US17731583

申请日：2022-04-28

Applicant: SanDisk Technologies LLC

Inventor： Kiyohiko Sakakibara ,  Ken Oowada

IPC: G11C5/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L27/11582 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  G11C16/26 ,  H01L21/8234

Abstract: A non-volatile memory device is provided that includes an alternating stack of conducting layers and dielectric layers, a charge trap layer, a layer of polysilicon, and a tunneling dielectric layer arranged between the charge trap layer and the layer of polysilicon. The charge trap layer extends through the alternating stack of conducting layers and dielectric layers. The layer of polysilicon includes a first portion having a first thickness and a second portion having a second thickness that is greater than the first thickness. The second portion is arranged below the alternating stack of conducting layers and dielectric layers.

公开(公告)号：US11348649B2

公开(公告)日：2022-05-31

申请号：US16909826

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Hiroki Yabe ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157 ,  G11C16/24 ,  G11C16/34 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US11049580B1

公开(公告)日：2021-06-29

申请号：US16914408

申请日：2020-06-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Ken Oowada

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.

公开(公告)号：US11004525B1

公开(公告)日：2021-05-11

申请号：US16796897

申请日：2020-02-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rajdeep Gautam ,  Ken Oowada

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519

Abstract: Systems and methods for increasing cycling endurance and minimizing over programming of non-volatile memory cells by modulating the programming voltage applied to the non-volatile memory cells over time as the number of program/erase cycles increases are described. A bit count ratio based on bit counts within two threshold voltage zones may be used to determine the amount of voltage reduction in the programming voltage applied during subsequent programming operations. For example, if the bit count ratio is between 0.02 and 0.05, then the reduction in the programming voltage may be 100 mV; if the bit count ratio is between 0.05 and 0.10, then the reduction in the programming voltage may be 200 mV. The modulation (e.g., the reduction) of the programming voltage may be performed at varying cycle intervals depending on the total number of program/erase cycles for a memory block and/or the bit count ratio.

公开(公告)号：US20210125643A1

公开(公告)日：2021-04-29

申请号：US16666077

申请日：2019-10-28

Applicant: SanDisk Technologies LLC

Inventor： Kiyohiko Sakakibara ,  Ken Oowada

IPC: G11C5/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: Methods for reducing manufacturing cost and improving the reliability of non-volatile memories using NAND strings with polysilicon channels and p-type doped source lines are described. A NAND string may include a polysilicon channel that is orthogonal to a substrate and connects to a boron doped source line at a source-side end of the NAND string. To reduce the likelihood of the polysilicon channel being cut-off or pinched near the source-side end of the NAND string, a thicker polysilicon channel may be formed near the source-side end of the NAND string while a thinner polysilicon channel may be formed for the remainder of the NAND string by diffusing boron into a first portion of the polysilicon channel corresponding with the thicker polysilicon channel and then etching the polysilicon channel with etchants that exhibit a reduction in their etch rate at a boron concentration above a threshold concentration.

公开(公告)号：US10957401B2

公开(公告)日：2021-03-23

申请号：US16909832

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/08 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US11342028B2

公开(公告)日：2022-05-24

申请号：US17227820

申请日：2021-04-12

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US11227663B2

公开(公告)日：2022-01-18

申请号：US17173023

申请日：2021-02-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Ippei Yasuda ,  Ken Oowada ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519

Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.

公开(公告)号：US11094715B2

公开(公告)日：2021-08-17

申请号：US16919744

申请日：2020-07-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Ken Oowada

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L23/528 ,  H01L21/311 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L21/28 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/36 ,  H01L21/306

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The alternating stack includes a first region in which all layers of the alternating stack are present and a second region in which at least a topmost one of the electrically conductive layers is absent. First memory opening fill structures extend through the first region of the alternating stack, and second memory opening fill structures extend through the second region of the alternating stack. The first memory opening fill structures have a greater height than the second memory opening fill structures. Pocket doping regions extending over a respective subset of topmost electrically conductive layers for the memory opening fill structures can be formed to provide higher threshold voltages and to enable selective activation of vertical semiconductor channels connected a same bit line.