公开(公告)号：US11798638B2

公开(公告)日：2023-10-24

申请号：US17484218

申请日：2021-09-24

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459 ,  H01L25/0657 ,  H01L2225/06562 ,  H10B43/10 ,  H10B43/27

Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.

公开(公告)号：US20230326531A1

公开(公告)日：2023-10-12

申请号：US17718124

申请日：2022-04-11

Applicant: SanDisk Technologies LLC

Inventor： Yanjie Wang ,  Ohwon Kwon ,  Kou Tei ,  Tai-Yuan Tseng ,  Yasue Yamamoto ,  Yonggang Wu ,  Guirong Liang

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3459 ,  H01L25/0657

Abstract: Technology is disclosed herein for a memory system having a dynamic supply voltage to sense amplifiers. In an aspect, the supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

公开(公告)号：US20230326530A1

公开(公告)日：2023-10-12

申请号：US17715647

申请日：2022-04-07

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Kou Tei ,  Deepanshu Dutta ,  Hiroyuki Mizukoshi ,  Jiahui Yuan ,  Xiang Yang

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C11/5621

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.

公开(公告)号：US20230101019A1

公开(公告)日：2023-03-30

申请号：US17484218

申请日：2021-09-24

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Kou Tei ,  Ohwon Kwon

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56

Abstract: Technology for mitigating interference to select transistors in 3D memory is disclosed. In one aspect, a control circuit pre-charges a first set of bit lines to a first voltage and pre-charges a second set of bit lines to a second voltage greater than the first voltage. The control circuit may increase the voltage on the first set of bit lines to the second voltage while the second set of bit lines are floating to couple up the voltages on the second set of bit lines to a voltage greater than the second voltage. The higher voltage on the second set of bit lines compensates for interference that some of the select transistors may experience from an adjacent select line. For example, the higher voltage can prevent a leakage current in the select transistors from occurring. Preventing the leakage current can improve boosting of NAND channel voltages, thereby preventing program disturb.

公开(公告)号：US11521675B1

公开(公告)日：2022-12-06

申请号：US17349009

申请日：2021-06-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kou Tei ,  Anirudh Amarnath ,  Ohwon Kwon

IPC: G11C7/00 ,  G11C11/4096 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408

Abstract: A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.

公开(公告)号：US20210104271A1

公开(公告)日：2021-04-08

申请号：US16593576

申请日：2019-10-04

Applicant: SanDisk Technologies LLC

Inventor： Ohwon Kwon ,  Kou Tei ,  VSNK Chaitanya G.

IPC: G11C11/4074 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/56

Abstract: A memory device is provided including physical block circuitry including a first lateral network arrangement and a second lateral network arrangement. Each of the first and second lateral network arrangements includes a single generator configured to output both a sense amplifier voltage VHSA and a data latch voltage VDDSA, in each of a first mode and a second mode. In the first mode, during which read and program verify and other operations may occur, the generator receives VHSA as a feedback signal and in the second mode, during which programming, POR, and EVFY operations may occur, the generator receives VDDSA as a feedback signal.