公开(公告)号：US12142315B2

公开(公告)日：2024-11-12

申请号：US17825193

申请日：2022-05-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Muhammad Masuduzzaman ,  Jiacen Guo

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10

Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.

公开(公告)号：US20230307072A1

公开(公告)日：2023-09-28

申请号：US17701365

申请日：2022-03-22

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta ,  Gerrit Jan Hemink

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11556

Abstract: The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or discharges a sense node through a channel including the at least one memory cell and compares a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.

公开(公告)号：US20220399066A1

公开(公告)日：2022-12-15

申请号：US17347772

申请日：2021-06-15

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Dengtao Zhao ,  Anubhav Khandelwal ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/28 ,  G11C16/08

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.

公开(公告)号：US11417393B2

公开(公告)日：2022-08-16

申请号：US17142753

申请日：2021-01-06

Applicant: SanDisk Technologies LLC

Inventor： Sujjatul Islam ,  Muhammad Masuduzzaman ,  Ravi Kumar

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10

Abstract: A method for programming a non-volatile memory structure with four-page data, wherein the method comprises, in a first stage, selecting four programmable states of a segment of MLC NAND-type memory cells, programming at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increasing the first step voltage level to a second step voltage level for a single program pulse and according to a pre-determined magnitude, and programming a latter of the at least two neighboring programmable states at the first step voltage level.

公开(公告)号：US11139038B1

公开(公告)日：2021-10-05

申请号：US16903575

申请日：2020-06-17

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/14 ,  H01L27/11556

Abstract: A method for programming a target memory cell of a memory array of a non-volatile memory system, the method comprising performing a read operation of one or more memory cells neighboring a target memory cell, thereby determining a data pattern of the one or more neighboring memory cells, storing the data pattern and, during a program operation of the target memory cell, adjusting a verify voltage level according to the stored data pattern of the one or more neighboring memory cells.

公开(公告)号：US11081184B2

公开(公告)日：2021-08-03

申请号：US16701450

申请日：2019-12-03

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/12 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/24 ,  G11C13/00 ,  G11C16/04

Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.

公开(公告)号：US10984876B2

公开(公告)日：2021-04-20

申请号：US16445367

申请日：2019-06-19

Applicant: SanDisk Technologies LLC

Inventor： Piyush Dak ,  Mohan Dunga ,  Chao Qin ,  Muhammad Masuduzzaman ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.

公开(公告)号：US09779832B1

公开(公告)日：2017-10-03

申请号：US15371462

申请日：2016-12-07

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta ,  Jong Yuh

IPC: G11C7/10 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/16 ,  G11C16/08 ,  G11C7/22

CPC classification number: G11C16/3459 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3495

Abstract: In one aspect, a voltage is provided as a rectangular waveform in which the duty cycle is varied to provide different effective voltages. These voltages may be applied to various control lines in a memory device such as a word line, bit line and/or source line, in a program, verify, read or erase operation. In some cases, the duty cycle is a function of programming data of a memory cell such as an assigned data state or a programming speed category. The duty cycle could also be a function of a programming phase or other criterion. The duty cycle can be varied by modifying the duration and separation of the pulses of the waveform or by pulse counting, in which a specified number of pulses are passed in a time period.

公开(公告)号：US12057175B2

公开(公告)日：2024-08-06

申请号：US17715647

申请日：2022-04-07

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Kou Tei ,  Deepanshu Dutta ,  Hiroyuki Mizukoshi ,  Jiahui Yuan ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  G11C11/5621 ,  G11C11/5671

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.

公开(公告)号：US12057168B2

公开(公告)日：2024-08-06

申请号：US16899860

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3459 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N−1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line. Determining the data states, determining the program voltage configuration, and performing the program operation may be repeated until a program stop condition is satisfied.