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    THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF
    11.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF 有权

    公开(公告)号：US20220068966A1

    公开(公告)日：2022-03-03

    申请号：US17362034

    申请日：2021-06-29

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

    IPC: H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L29/24 ,  H01L27/11556 ,  H01L21/02 ,  H01L25/00

    Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom electrode, a metal oxide semiconductor vertical transistor channel, a cylindrical gate dielectric, and a top electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

    BONDED DIE ASSEMBLY CONTAINING PARTIALLY FILLED THROUGH-SUBSTRATE VIA STRUCTURES AND METHODS FOR MAKING THE SAME
    13.
    发明申请
    BONDED DIE ASSEMBLY CONTAINING PARTIALLY FILLED THROUGH-SUBSTRATE VIA STRUCTURES AND METHODS FOR MAKING THE SAME 有权

    公开(公告)号：US20210028148A1

    公开(公告)日：2021-01-28

    申请号：US16521849

    申请日：2019-07-25

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Chen WU ,  Peter RABKIN ,  Yangyin CHEN ,  Masaaki HIGASHITANI

    IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

    Abstract: A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure.

    THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF
    17.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH VERTICAL FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF 有权

    公开(公告)号：US20220068903A1

    公开(公告)日：2022-03-03

    申请号：US17007823

    申请日：2020-08-31

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Kwang-Ho KIM ,  Peter RABKIN

    IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

    Abstract: A semiconductor structure includes at least one set of vertical field effect transistors embedded within dielectric material layers overlying a substrate. Each vertical field effect transistor includes a bottom doped semiconductor electrode, a vertical transistor channel, a cylindrical gate dielectric, and a top doped semiconductor electrode. A three-dimensional NAND memory array can be provided over the first field effect transistors, and can be electrically connected to the vertical field effect transistors via metal interconnect structures. Alternatively, a three-dimensional NAND memory array can be formed on another substrate, which can be bonded to the substrate via metal-to-metal bonding. The vertical field effect transistors can be employed as switches for bit lines, word lines, or other components of the three-dimensional NAND memory array.

    FERROELECTRIC MEMORY DEVICES WITH DUAL DIELECTRIC CONFINEMENT AND METHODS OF FORMING THE SAME
    20.
    发明申请
    FERROELECTRIC MEMORY DEVICES WITH DUAL DIELECTRIC CONFINEMENT AND METHODS OF FORMING THE SAME 有权

    公开(公告)号：US20210091204A1

    公开(公告)日：2021-03-25

    申请号：US16577176

    申请日：2019-09-20

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Peter RABKIN ,  Masaaki HIGASHITANI

    IPC: H01L29/51 ,  H01L29/417 ,  H01L21/28 ,  H01L27/11514

    Abstract: A semiconductor structure contains a semiconductor channel extending between a source region and a drain region, at least one gate electrode, a ferroelectric material portion located between the semiconductor channel and the at least one gate electrode, a front-side gate dielectric located between the ferroelectric material portion and the semiconductor channel, and a backside gate dielectric located between the ferroelectric material portion and the at least one gate electrode. The front-side gate dielectric and the backside gate dielectric have a dielectric constant greater than 7.9 and a band gap greater than a band gap of the ferroelectric material portion.

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