公开(公告)号：US20210408019A1

公开(公告)日：2021-12-30

申请号：US16913717

申请日：2020-06-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Johann ALSMEIER

IPC: H01L27/11507 ,  H01L27/22 ,  H01L43/12 ,  H01L27/24 ,  H01L45/00

Abstract: At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.

公开(公告)号：US20210407943A1

公开(公告)日：2021-12-30

申请号：US17406758

申请日：2021-08-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Joyeeta NAG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A memory device includes a first electrically conductive line laterally extending along a first horizontal direction, a memory pillar structure overlying and contacting the first electrically conductive line, the memory pillar structure includes a vertical stack of a ferroelectric material plate and a selector material plate, and a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure.

公开(公告)号：US20210327889A1

公开(公告)日：2021-10-21

申请号：US16849600

申请日：2020-04-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Yao-Sheng LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  H01L29/423

Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.

公开(公告)号：US20210296285A1

公开(公告)日：2021-09-23

申请号：US16825397

申请日：2020-03-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Adarsh RAJASHEKHAR ,  Senaka KANAKAMEDALA ,  Fei ZHOU

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

公开(公告)号：US20210296269A1

公开(公告)日：2021-09-23

申请号：US17118036

申请日：2020-12-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L23/00 ,  H01L23/495

Abstract: A bonded assembly includes a first semiconductor die that includes first semiconductor devices, and a first pad-level dielectric layer and embedding first bonding pads; and a second semiconductor die that includes second semiconductor devices, and a second pad-level dielectric layer embedding second bonding pads that includes a respective second pad base portion. Each of the first bonding pads includes a respective first pad base portion and a respective first metal alloy material portion having a higher coefficient of thermal expansion (CTE) than the respective first pad base portion. Each of the second bonding pads is bonded to a respective one of the first bonding pads.

公开(公告)号：US20210265385A1

公开(公告)日：2021-08-26

申请号：US17001003

申请日：2020-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Rahul SHARANGPANI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11543

Abstract: A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.

公开(公告)号：US20210210497A1

公开(公告)日：2021-07-08

申请号：US16737088

申请日：2020-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seung-Yeul YANG ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI

IPC: H01L27/11514 ,  H01L49/02 ,  H01L45/00 ,  H01L23/528 ,  H01L27/11504

Abstract: A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.

公开(公告)号：US20210183882A1

公开(公告)日：2021-06-17

申请号：US16710481

申请日：2019-12-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli ZHANG ,  Dong-il MOON ,  Raghuveer S. MAKALA ,  Peng ZHANG ,  Wei ZHAO ,  Ashish BARASKAR

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/532 ,  H01L21/311 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  H01L23/528

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

公开(公告)号：US20210082955A1

公开(公告)日：2021-03-18

申请号：US16568668

申请日：2019-09-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Seung-Yeul YANG ,  Fei ZHOU

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.

公开(公告)号：US20210028135A1

公开(公告)日：2021-01-28

申请号：US16851908

申请日：2020-04-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L23/00 ,  H01L25/18

Abstract: At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.