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公开(公告)号：US11081193B1
公开(公告)日：2021-08-03
申请号：US16903274
申请日：2020-06-16
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang
Abstract: Technology is disclosed herein for correcting skew between data signals and a clock signal. In one aspect, a memory system has a delay circuit having delay blocks, with each delay block having one or more inverters. The delay circuit is configured to pass a data signal through either an odd number of the inverters or an even number of the inverters to produce a delayed data signal. The memory system has a skew correction circuit configured to control the number of inverters in the delay circuit through which the data signal is passed in order to correct skew between the data signal and the clock signal. The memory system has a polarity correction circuit configured to invert the data signal in the event that the delay circuit passed the data signal through the odd number of the inverters.
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公开(公告)号：US20190109585A1
公开(公告)日：2019-04-11
申请号：US15875519
申请日：2018-01-19
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra , Srinivas Rajendra
IPC: H03K3/017 , H03K17/687 , H03M1/66
Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.
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公开(公告)号：US20210304834A1
公开(公告)日：2021-09-30
申请号：US16828547
申请日：2020-03-24
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra
Abstract: Technology is disclosed herein for a semiconductor die, and controlling operation of the semiconductor die. In some aspects, a semiconductor die is configured to test an I/O circuit on the semiconductor die. The semiconductor die has an input circuit that compares a voltage signal at one of a first input or a second input with a reference voltage at the other of the first input or the second input to generate an input voltage signal. The first input may be connected to an I/O contact. During a normal mode a control circuit on the die provides a reference voltage to second input. During a test mode, the control circuit internally loops back a test signal from an output circuit to the second input of the input circuit. Thus, the test signal avoids the I/O contact.
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公开(公告)号：US10530347B2
公开(公告)日：2020-01-07
申请号：US16017286
申请日：2018-06-25
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra
Abstract: A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.
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Patent Agency Ranking
公开(公告)号：US10528255B2
公开(公告)日：2020-01-07
申请号：US15365944
申请日：2016-11-30
Applicant: SanDisk Technologies LLC
Inventor： Jiwang Lee , Anil Pai , Tianyu Tang , Ravindra Arjun Madpur , Amandeep Kaur , Ragul Kumar Krishnan , Venkata Kolagatla
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for accessing non-volatile memory. An apparatus includes one or more memory die. A memory die includes an array of non-volatile memory cells, a set of ports, and an on-die controller. The set of ports includes a first port and a second port. The first port includes a first plurality of electrical contacts and the second port includes a second plurality of electrical contacts. The on-die controller communicates via the set of ports to receive command and address information and to transfer data for a data operation on the array of non-volatile memory cells. The on-die controller uses the first port and the second port in a first mode and uses the first port without the second port in a second mode. The second mode provides compatibility with an interface of a legacy type of memory die.
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公开(公告)号：US20190333551A1
公开(公告)日：2019-10-31
申请号：US15965099
申请日：2018-04-27
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra
IPC: G11C7/22 , H03K5/133 , H03K3/037 , H03K5/1534 , H03K3/017
Abstract: A duty cycle correction system corrects for duty cycle distortion by measuring average time interval durations of consecutive intervals of an input signal. The system generates complementary ramp signals that have cross-points indicating midpoints of the intervals, and detects those cross-points. An output circuit of the duty cycle correction system generates an output signal that performs rising and falling transitions in response to the detected cross-points.
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公开(公告)号：US20190296723A1
公开(公告)日：2019-09-26
申请号：US16017286
申请日：2018-06-25
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra
Abstract: A skew correction system includes delay circuits positioned in front of sampling circuitry. A skew correction controller first delays an input clock signal to create hold violations. Then with, with the delay of an input clock signal fixed at a reference delay amount, the skew correction controller delays input data signals first to remove or reduce the hold violations, and then to create setup violations. Based on the delaying, the skew correction controller identifies data valid windows for the input data signals, and in turn, identifies target delay amounts that position a delayed clock signal in target sampling positions.
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公开(公告)号：US20190109584A1
公开(公告)日：2019-04-11
申请号：US15875400
申请日：2018-01-19
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra , Srinivas Rajendra
IPC: H03K3/017 , H03K17/687 , H03M1/66
Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.
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公开(公告)号：US09673798B1
公开(公告)日：2017-06-06
申请号：US15226574
申请日：2016-08-02
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra , Srinivas Rajendra
CPC classification number: H03K5/1565 , G11C7/222 , G11C13/0021 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/0483 , G11C16/32 , G11C2207/2254 , G11C2213/71 , G11C2213/75 , G11C2213/77
Abstract: Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.
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