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公开(公告)号：US20230386600A1
公开(公告)日：2023-11-30
申请号：US17828708
申请日：2022-05-31
Applicant: SanDisk Technologies LLC
Inventor： Jang Woo Lee , Srinivas Rajendra , Anil Pai , Venkatesh Prasad Ramachandra
Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.
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公开(公告)号：US11829281B2
公开(公告)日：2023-11-28
申请号：US17348910
申请日：2021-06-16
Applicant: SanDisk Technologies LLC
Inventor： Jang Woo Lee , Srinivas Rajendra , Anil Pai , Venkatesh Ramachandra
IPC: G06F11/36 , G11C7/10 , G06F18/214 , G06F13/16 , G06F3/06
CPC classification number: G06F11/368 , G06F13/1689 , G06F18/214 , G11C7/1096 , G06F3/061 , G11C2207/2254
Abstract: Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.
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公开(公告)号：US10587247B2
公开(公告)日：2020-03-10
申请号：US15875519
申请日：2018-01-19
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra , Srinivas Rajendra
IPC: H03K3/017 , H03K17/687 , H03M1/66
Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.
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公开(公告)号：US20220405190A1
公开(公告)日：2022-12-22
申请号：US17348910
申请日：2021-06-16
Applicant: SanDisk Technologies LLC
Inventor： Jang Woo Lee , Srinivas Rajendra , Anil Pai , Venkatesh Ramachandra
Abstract: Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.
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公开(公告)号：US20200076412A1
公开(公告)日：2020-03-05
申请号：US16206321
申请日：2018-11-30
Applicant: SanDisk Technologies LLC
Inventor： Srinivas Rajendra , Tianyu Tang , Venkatesh Ramachandra
IPC: H03K5/156 , H03K5/134 , G11C7/22 , G11C11/4076 , H01L27/11524
Abstract: A duty cycle correction circuit includes an AND/OR logic circuit that reduces duty cycle distortion in a pair of input signals. The AND/OR logic circuit includes a first push-pull circuit configured to generate a first output signal in response to receipt of a first pair of delayed input signals, and a second push-pull circuit configured to generate a second output signal in response to receipt of a second pair of delayed input signals. The first and second push-pull circuits may have matching beta ratios. Additionally, a latch is coupled to output nodes of the first and second push-pull circuits. The latch is configured to maintain magnitude levels at the output nodes during delay offset periods of the first and second pairs of delayed input signals.
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Patent Agency Ranking
公开(公告)号：US10284182B2
公开(公告)日：2019-05-07
申请号：US15639153
申请日：2017-06-30
Applicant: SanDisk Technologies LLC
Inventor： Primit Modi , Venkatesh Ramachandra , Tianyu Tang , Srinivas Rajendra
Abstract: A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.
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公开(公告)号：US20180175834A1
公开(公告)日：2018-06-21
申请号：US15639153
申请日：2017-06-30
Applicant: SanDisk Technologies LLC
Inventor： Primit Modi , Venkatesh Ramachandra , Tianyu Tang , Srinivas Rajendra
CPC classification number: H03K3/017 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , G11C29/023 , G11C29/028 , H03K5/151 , H03K5/1565 , H03K7/08
Abstract: A complementary signal path may include an amplifier circuit configured to receive a pair of complementary input signals and a data alignment circuit configured to output a pair of complementary output signals in response to the pair of complementary input signals. A control circuit may detect duty cycle distortion in the pair of complementary output signals and perform a duty cycle correction process to remove the distortion. To do so, the control circuit may search for target current amounts in response to the duty cycle distortion and inject a control current into the amplifier circuit at the target current amounts.
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公开(公告)号：US12100458B2
公开(公告)日：2024-09-24
申请号：US17827562
申请日：2022-05-27
Applicant: SanDisk Technologies LLC
Inventor： Venkatesh Prasad Ramachandra , Jang Woo Lee , Srinivas Rajendra , Anil Pai
IPC: G11C16/32
CPC classification number: G11C16/32
Abstract: Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.
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公开(公告)号：US20190109584A1
公开(公告)日：2019-04-11
申请号：US15875400
申请日：2018-01-19
Applicant: SanDisk Technologies LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra , Srinivas Rajendra
IPC: H03K3/017 , H03K17/687 , H03M1/66
Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.
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公开(公告)号：US09673798B1
公开(公告)日：2017-06-06
申请号：US15226574
申请日：2016-08-02
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Tianyu Tang , Venkatesh Ramachandra , Srinivas Rajendra
CPC classification number: H03K5/1565 , G11C7/222 , G11C13/0021 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C16/0483 , G11C16/32 , G11C2207/2254 , G11C2213/71 , G11C2213/75 , G11C2213/77
Abstract: Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.
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