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    Chip select, command, and address encoding
    1.
    发明授权
    Chip select, command, and address encoding 有权

    公开(公告)号：US12057189B2

    公开(公告)日：2024-08-06

    申请号：US17828921

    申请日：2022-05-31

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang ,  Siddhesh Darne ,  Venkatesh Prasad Ramachandra

    IPC: G11C7/10 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12

    CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12

    Abstract: A command/address sequence associated with a read/write operation for a memory device utilizes various existing command/address clock signals in a novel way that obviates the need to utilize the I/O bus. As such, the command/address sequence can be performed in parallel with the DIN/DOUT operations, thereby removing the performance bottleneck that would otherwise be caused by the command and address sequencing. The command/address sequence encodes bit information on first and second enable signals and utilizes rising or falling edges of a clock signal to latch the encoded bit information, which can then be decoded to determine corresponding command and address codes. A chip select sequence is also disclosed that enables a memory chip configuration to be employed in which each chip in a package shares a common connection to a controller but does not require hard-coded pins for performing chip select.

    DUTY CYCLE CORRECTION FOR COMPLEMENTARY CLOCK SIGNALS
    3.
    发明申请
    DUTY CYCLE CORRECTION FOR COMPLEMENTARY CLOCK SIGNALS 审中-公开

    公开(公告)号：US20200076412A1

    公开(公告)日：2020-03-05

    申请号：US16206321

    申请日：2018-11-30

    Applicant: SanDisk Technologies LLC

    Inventor： Srinivas Rajendra ,  Tianyu Tang ,  Venkatesh Ramachandra

    IPC: H03K5/156 ,  H03K5/134 ,  G11C7/22 ,  G11C11/4076 ,  H01L27/11524

    Abstract: A duty cycle correction circuit includes an AND/OR logic circuit that reduces duty cycle distortion in a pair of input signals. The AND/OR logic circuit includes a first push-pull circuit configured to generate a first output signal in response to receipt of a first pair of delayed input signals, and a second push-pull circuit configured to generate a second output signal in response to receipt of a second pair of delayed input signals. The first and second push-pull circuits may have matching beta ratios. Additionally, a latch is coupled to output nodes of the first and second push-pull circuits. The latch is configured to maintain magnitude levels at the output nodes during delay offset periods of the first and second pairs of delayed input signals.

    Duty cycle correction on an interval-by-interval basis
    4.
    发明授权
    Duty cycle correction on an interval-by-interval basis 有权

    公开(公告)号：US10447247B1

    公开(公告)日：2019-10-15

    申请号：US15965099

    申请日：2018-04-27

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang ,  Venkatesh Ramachandra

    IPC: H03K3/017 ,  G11C7/22

    Abstract: A duty cycle correction system corrects for duty cycle distortion by measuring average time interval durations of consecutive intervals of an input signal. The system generates complementary ramp signals that have cross-points indicating midpoints of the intervals, and detects those cross-points. An output circuit of the duty cycle correction system generates an output signal that performs rising and falling transitions in response to the detected cross-points.

    Dynamic clock mask based on read data for power saving
    7.
    发明授权
    Dynamic clock mask based on read data for power saving 有权

    公开(公告)号：US12283341B2

    公开(公告)日：2025-04-22

    申请号：US18353709

    申请日：2023-07-17

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang

    IPC: G11C7/10 ,  G11C7/22

    Abstract: Systems and methods disclosed herein provide for reduced power composition during data read operations from memory devices through gating of clock signals based on a bit pattern of data to be read from the memory device. Example devices and methods disclosed herein comprise receiving a command to read data from a memory structure of the memory device and latching a bit pattern of the data from the memory structure to a data register based on the received command. The disclose systems and methods use the bit pattern to generate a clock mask according to similarities between bit values within the bit pattern. When a read enable signal is detected on a read enable interface of the embodiments disclosed herein, the clock mask is gated based on the clock mask, and bit values are latched to an input/output interface of the memory device in accordance with the gated read enable signal.

    Receiver side setup and hold calibration
    8.
    发明授权
    Receiver side setup and hold calibration 有权

    公开(公告)号：US11901905B2

    公开(公告)日：2024-02-13

    申请号：US17667451

    申请日：2022-02-08

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang

    IPC: G11C7/22 ,  H03L7/081 ,  G06F13/42 ,  G06F13/40

    CPC classification number: H03L7/0814 ,  G06F13/4022 ,  G06F13/4221 ,  G11C7/222

    Abstract: The present disclosure provides for calibrating clock signals in an unmatched data input system. In various embodiments, an unmatched data input system uses multi-delay circuits to calibrate a clock signal distributed to various input/outputs in the unmatched data input system. These multi-delay circuits can include coarse delay circuits and fine delay circuits that provide a broad range as well as accurate delay capabilities. Through the use of these multi-delay circuits, the unmatched data input system can optimally align a clock signal with its associated data signal across multiple input/outputs.

    Duty cycle and vox correction for complementary signals
    9.
    发明授权
    Duty cycle and vox correction for complementary signals 有权

    公开(公告)号：US10587247B2

    公开(公告)日：2020-03-10

    申请号：US15875519

    申请日：2018-01-19

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang ,  Venkatesh Ramachandra ,  Srinivas Rajendra

    IPC: H03K3/017 ,  H03K17/687 ,  H03M1/66

    Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.

    RECEIVER SIDE SETUP AND HOLD CALIBRATION
    10.
    发明公开
    RECEIVER SIDE SETUP AND HOLD CALIBRATION 审中-公开

    公开(公告)号：US20230253969A1

    公开(公告)日：2023-08-10

    申请号：US17667451

    申请日：2022-02-08

    Applicant: SanDisk Technologies LLC

    Inventor： Tianyu Tang

    IPC: H03L7/081 ,  G11C7/22 ,  G06F13/40 ,  G06F13/42

    CPC classification number: H03L7/0814 ,  G11C7/222 ,  G06F13/4022 ,  G06F13/4221

    Abstract: The present disclosure provides for calibrating clock signals in an unmatched data input system. In various embodiments, an unmatched data input system uses multi-delay circuits to calibrate a clock signal distributed to various input/outputs in the unmatched data input system. These multi-delay circuits can include coarse delay circuits and fine delay circuits that provide a broad range as well as accurate delay capabilities. Through the use of these multi-delay circuits, the unmatched data input system can optimally align a clock signal with its associated data signal across multiple input/outputs.

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