公开(公告)号：US20140339539A1

公开(公告)日：2014-11-20

申请号：US14272759

申请日：2014-05-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Kenichi OKAZAKI ,  Masahiko HAYAKAWA ,  Shinpei MATSUDA

IPC: H01L29/786

CPC classification number: H01L29/78606 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/4908 ,  H01L29/7869

Abstract: A semiconductor device including a transistor having excellent electrical characteristics is provided. Alternatively, a semiconductor device having a high aperture ratio and including a capacitor capable of increasing capacitance is provided. The semiconductor device includes a gate electrode, an oxide semiconductor film overlapping the gate electrode, an oxide insulating film in contact with the oxide semiconductor film, a first oxygen barrier film between the gate electrode and the oxide semiconductor film, and a second oxygen barrier film in contact with the first oxygen barrier film. The oxide semiconductor film and the oxide insulating film are provided on an inner side of the first oxygen barrier film and the second oxygen barrier film.

Abstract translation: 提供了包括具有优异电特性的晶体管的半导体器件。 或者，提供具有高开口率并且包括能够增加电容的电容器的半导体器件。 半导体器件包括栅电极，与栅电极重叠的氧化物半导体膜，与氧化物半导体膜接触的氧化物绝缘膜，栅电极和氧化物半导体膜之间的第一氧阻隔膜，以及第二氧阻隔膜 与第一氧阻隔膜接触。 氧化物半导体膜和氧化物绝缘膜设置在第一氧阻隔膜和第二氧阻隔膜的内侧。

公开(公告)号：US20250017041A1

公开(公告)日：2025-01-09

申请号：US18895584

申请日：2024-09-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Shinpei MATSUDA ,  Takuya KAWATA

IPC: H10K59/121 ,  H10K50/822 ,  H10K50/854 ,  H10K50/858 ,  H10K59/40 ,  H10K71/80

Abstract: A light-emitting device, a lighting device, a display device, or the like in which the state of a back surface side can be observed when light is not emitted is provided. The light-emitting device includes a plurality of light-emitting portions and a region transmitting visible light in a region other than the light-emitting portions. Alternatively, the light-emitting device includes a plurality of light-transmitting portions transmitting visible light and a light-emitting portion that can emit light in a region other than the light-transmitting portions. When light is not emitted, the state of a back surface side of the light-emitting device is visible through the region transmitting visible light. When light is emitted, the state of the back surface side of the light-emitting device can be made less visible by diffusion of light emitted from the light-emitting portion.

公开(公告)号：US20240355930A1

公开(公告)日：2024-10-24

申请号：US18626777

申请日：2024-04-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuya HANAOKA ,  Daisuke MATSUBAYASHI ,  Yoshiyuki KOBAYASHI ,  Shunpei YAMAZAKI ,  Shinpei MATSUDA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/785 ,  H01L29/7854

Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.

公开(公告)号：US20210273068A1

公开(公告)日：2021-09-02

申请号：US17324386

申请日：2021-05-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio SUZUKI ,  Shinpei MATSUDA ,  Shunpei YAMAZAKI

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L27/1156 ,  H01L29/788 ,  H01L21/28 ,  H01L29/778 ,  H01L29/06 ,  H01L29/775

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

公开(公告)号：US20190035936A1

公开(公告)日：2019-01-31

申请号：US16133814

申请日：2018-09-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Shinpei MATSUDA

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/04

Abstract: The semiconductor device includes a first insulating layer; a first oxide semiconductor; a first insulator containing indium, an element M (M is gallium, aluminum, titanium, yttrium, or tin), and zinc; a second oxide semiconductor; a source electrode layer; a drain electrode layer; a second insulator containing indium, the element M, and zinc; a gate insulating layer; and a gate electrode layer. The first and second oxide semiconductors each include a region with c-axis alignment. In the first and second oxide semiconductors, the number of indium atoms divided by sum of numbers of the indium atoms, element M atoms, and zinc atoms is ⅓ or more. In the first insulator, the number of zinc atoms divided by sum of the numbers of indium atoms, element M atoms, and zinc atoms is ⅓ or less.

公开(公告)号：US20170278874A1

公开(公告)日：2017-09-28

申请号：US15464534

申请日：2017-03-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Junichi KOEZUKA ,  Kenichi OKAZAKI ,  Yukinori SHIMA ,  Shinpei MATSUDA ,  Haruyuki BABA ,  Ryunosuke HONDA

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/127 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7786 ,  H01L29/7869 ,  H01L29/78696

Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.

公开(公告)号：US20170040348A1

公开(公告)日：2017-02-09

申请号：US15296395

申请日：2016-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hiroyuki MIYAKE ,  Kenichi OKAZAKI ,  Masahiko HAYAKAWA ,  Shinpei MATSUDA

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1368

CPC classification number: H01L27/1225 ,  G02F1/134309 ,  G02F1/1368 ,  H01L27/1237 ,  H01L27/124 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided. Further, a semiconductor device including a transistor having excellent electrical characteristics is provided. The semiconductor device includes a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode; gate insulating films are provided between the oxide semiconductor film and the first gate electrode and between the oxide semiconductor film and the second gate electrode; and in the channel width direction of the transistor, the first or second gate electrode faces a side surface of the oxide semiconductor film with the gate insulating film between the oxide semiconductor film and the first or second gate electrode.

Abstract translation: 提供了一种半导体器件，其包括氧化物半导体，并且其中抑制了由于栅极BT应力而形成的寄生沟道。 此外，提供了包括具有优异电特性的晶体管的半导体器件。 半导体器件包括具有双栅极结构的晶体管，其中氧化物半导体膜设置在第一栅电极和第二栅电极之间; 在所述氧化物半导体膜和所述第一栅电极之间以及所述氧化物半导体膜和所述第二栅电极之间设置栅绝缘膜; 并且在晶体管的沟道宽度方向上，第一或第二栅电极与氧化物半导体膜与第一或第二栅电极之间的栅极绝缘膜面对氧化物半导体膜的侧面。

公开(公告)号：US20160284862A1

公开(公告)日：2016-09-29

申请号：US15079684

申请日：2016-03-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Shinpei MATSUDA

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/78606 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: The semiconductor device includes a first insulating layer; a first oxide semiconductor; a first insulator containing indium, an element M (M is gallium, aluminum, titanium, yttrium, or tin), and zinc; a second oxide semiconductor; a source electrode layer; a drain electrode layer; a second insulator containing indium, the element M, and zinc; a gate insulating layer; and a gate electrode layer. The first and second oxide semiconductors each include a region with c-axis alignment. In the first and second oxide semiconductors, the number of indium atoms divided by sum of numbers of the indium atoms, element M atoms, and zinc atoms is ⅓ or more. In the first insulator, the number of zinc atoms divided by sum of the numbers of indium atoms, element M atoms, and zinc atoms is ⅓ or less.

Abstract translation: 半导体器件包括第一绝缘层; 第一氧化物半导体; 含有铟的第一绝缘体，元素M（M是镓，铝，钛，钇或锡）和锌; 第二氧化物半导体; 源电极层; 漏电极层; 包含铟的第二绝缘体，元素M和锌; 栅极绝缘层; 和栅电极层。 第一和第二氧化物半导体各自包括具有c轴对准的区域。 在第一和第二氧化物半导体中，铟原子数除以铟原子，元素M原子和锌原子的数量之和为1/3或更多。 在第一绝缘体中，锌原子数除以铟原子数，元素M原子和锌原子的数量之和为1/3或更小。

公开(公告)号：US20160013321A1

公开(公告)日：2016-01-14

申请号：US14788940

申请日：2015-07-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KOBAYASHI ,  Shinpei MATSUDA ,  Shunpei YAMAZAKI

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/0629 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/78696

Abstract: A semiconductor device having stable electric characteristics is provided. The transistor includes first to third oxide semiconductor layers, a gate electrode, and a gate insulating layer. The second oxide semiconductor layer has a portion positioned between the first and third oxide semiconductor layers. The gate insulating layer has a region in contact with a top surface of the third oxide semiconductor layer. The gate electrode overlaps with a top surface of the portion with the gate insulating layer positioned therebetween. The gate electrode faces a side surface of the portion in a channel width direction with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 8 nm. The length in the channel width direction of the second oxide semiconductor layer is less than 60 nm.

Abstract translation: 提供具有稳定电特性的半导体器件。 晶体管包括第一至第三氧化物半导体层，栅电极和栅极绝缘层。 第二氧化物半导体层具有位于第一和第三氧化物半导体层之间的部分。 栅极绝缘层具有与第三氧化物半导体层的顶表面接触的区域。 栅电极与栅绝缘层位于其间的部分的顶表面重叠。 栅极电极在栅极绝缘层位于沟槽宽度方向上面对该部分的侧面。 第二氧化物半导体层包括厚度大于或等于2nm且小于8nm的区域。 第二氧化物半导体层的沟道宽度方向的长度小于60nm。

公开(公告)号：US20160005871A1

公开(公告)日：2016-01-07

申请号：US14753426

申请日：2015-06-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinpei MATSUDA ,  Toshihiko TAKEUCHI ,  Daisuke MATSUBAYASHI

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: A transistor with a small subthreshold swing value is provided. A transistor with a low density of shallow interface states at an interface between a semiconductor and a gate insulator is provided. A transistor with favorable electrical characteristics is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. The semiconductor includes a region in which the semiconductor and the conductor overlap each other with the insulator positioned therebetween, and the density of shallow interface states at an interface between the semiconductor and the insulator in the region is lower than or equal to 1×1013 cm−2.

Abstract translation: 提供了具有小的亚阈值摆动值的晶体管。 提供了在半导体和栅极绝缘体之间的界面处具有低接合态的低密度晶体管。 提供具有良好电特性的晶体管。 半导体器件包括绝缘体，半导体和导体。 半导体包括半导体和导体彼此重叠的区域，绝缘体位于它们之间，并且该区域中的半导体与绝缘体之间的界面处的浅界面状态的密度低于或等于1×1013cm -2。