公开(公告)号：US20240021688A1

公开(公告)日：2024-01-18

申请号：US18371814

申请日：2023-09-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio SUZUKI ,  Shinpei MATSUDA ,  Shunpei YAMAZAKI

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/28 ,  H10B41/70 ,  H01L29/775 ,  H01L29/778 ,  H01L29/786 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L29/42324 ,  H01L29/0673 ,  H01L29/40114 ,  H01L29/42384 ,  H01L29/42392 ,  H10B41/70 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7869 ,  H01L29/7883 ,  H01L29/78696 ,  H01L29/66969

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

公开(公告)号：US20180013005A1

公开(公告)日：2018-01-11

申请号：US15697513

申请日：2017-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Haruyuki BABA ,  Akio SUZUKI ,  Hiromi SAWAI ,  Masahiko HAYAKAWA ,  Noritaka ISHIHARA ,  Masashi OOTA

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L21/203

CPC classification number: H01L29/7869 ,  H01L21/02266 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02609 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/203 ,  H01L27/1255 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696

Abstract: After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.

公开(公告)号：US20250132251A1

公开(公告)日：2025-04-24

申请号：US18989697

申请日：2024-12-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio SUZUKI ,  Atsushi MIYAGUCHI ,  Shunpei YAMAZAKI

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/367 ,  H10D30/67

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a silicon substrate and a device provided above the silicon substrate. The device includes a transistor and a conductor. The transistor includes a metal oxide in a channel formation region. Conductivity is imparted to the silicon substrate. The conductor is electrically connected to each of a drain of the transistor and the silicon substrate through an opening provided in the device. Heat of the drain of the transistor can be efficiently released through the silicon substrate.

公开(公告)号：US20200013865A1

公开(公告)日：2020-01-09

申请号：US16572673

申请日：2019-09-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio SUZUKI ,  Shinpei MATSUDA ,  Shunpei YAMAZAKI

IPC: H01L29/423 ,  H01L29/66

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

公开(公告)号：US20160155852A1

公开(公告)日：2016-06-02

申请号：US14953632

申请日：2015-11-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Haruyuki BABA ,  Akio SUZUKI ,  Hiromi SAWAI ,  Masahiko HAYAKAWA ,  Noritaka ISHIHARA ,  Masashi OOTA

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L29/24 ,  H01L29/04

CPC classification number: H01L29/7869 ,  H01L21/02266 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02609 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/203 ,  H01L27/1255 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696

Abstract: After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.

Abstract translation: 在溅射气体被供应到沉积室之后，在靶附近产生包括溅射气体的离子的等离子体。 溅射气体的离子被加速并与靶碰撞，使得靶板的平板粒子和原子与靶分离。 平板颗粒之间具有间隙而沉积，使得平面面向基板。 从目标分离的原子和原子团聚体进入沉积的平板颗粒之间的间隙，并在基板的平面方向上生长以填充间隙。 在衬底上形成膜。 在沉积之后，在氧气氛中在高温下进行热处理，其形成具有少量氧空位和高结晶度的氧化物。

公开(公告)号：US20230207567A1

公开(公告)日：2023-06-29

申请号：US17996516

申请日：2021-04-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuto YAKUBO ,  Shoki MIYATA ,  Akio SUZUKI ,  Takayuki IKEDA

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1207 ,  H01L29/7869 ,  H01L29/78681

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a current-to-voltage conversion portion, a current switch portion, a voltage-to-current conversion portion, and a control portion. The current switch portion includes a first transistor. The voltage-to-current conversion portion includes a second transistor. The control portion includes a third transistor. The first transistor includes an oxide semiconductor in a channel formation region. The second transistor includes a nitride semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. The first transistor is provided over a first substrate. The second transistor and the third transistor are provided over a second substrate.

公开(公告)号：US20220352384A1

公开(公告)日：2022-11-03

申请号：US17760836

申请日：2020-09-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi OOTA ,  Yoshinori ANDO ,  Shuhei NAGATSUKA ,  Tatsuki KOSHIDA ,  Satoru OHSHITA ,  Ryota HODO ,  Kazuki TSUDA ,  Akio SUZUKI

IPC: H01L29/786 ,  H01L27/108 ,  H01L29/66

Abstract: A semiconductor device that is suitable for high integration is provided. A first layer provided with a first transistor including an oxide semiconductor, over a substrate; a second layer over the first layer; a third layer provided with a second transistor including an oxide semiconductor, over the second layer; a fourth layer between the first layer and the second layer; and a fifth layer between the second layer and the third layer are included. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction, the total internal stress of the second layer acts in the direction opposite to the first direction, and the fourth layer and the fifth layer each include a film having a barrier property.

公开(公告)号：US20220020683A1

公开(公告)日：2022-01-20

申请号：US17297863

申请日：2019-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio SUZUKI ,  Atsushi MIYAGUCHI ,  Shunpei YAMAZAKI

IPC: H01L23/528 ,  H01L23/367 ,  H01L23/31 ,  H01L29/786

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a silicon substrate and a device provided above the silicon substrate. The device includes a transistor and a conductor. The transistor includes a metal oxide in a channel formation region. Conductivity is imparted to the silicon substrate. The conductor is electrically connected to each of a drain of the transistor and the silicon substrate through an opening provided in the device. Heat of the drain of the transistor can be efficiently released through the silicon substrate.

公开(公告)号：US20170062603A1

公开(公告)日：2017-03-02

申请号：US15251382

申请日：2016-08-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Akio SUZUKI ,  Shinpei MATSUDA ,  Shunpei YAMAZAKI

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/22 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/42324 ,  H01L27/1156 ,  H01L29/0673 ,  H01L29/40114 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/775 ,  H01L29/7786 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/7883

Abstract: A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

Abstract translation: 提供了耐短路效应的晶体管。 晶体管包括环状的第一导体，包括延伸穿过第一导体的环的内部的区域的氧化物半导体，第一导体和氧化物半导体之间的第一绝缘体，第一导体和第二导体之间的第二绝缘体 第一绝缘体，以及在第一导体的环内的电荷陷阱层。 电荷陷阱层位于第二绝缘体的内部并被配置成处于浮置状态。

公开(公告)号：US20230188094A1

公开(公告)日：2023-06-15

申请号：US17923653

申请日：2021-05-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Shoki MIYATA ,  Akio SUZUKI ,  Takayuki IKEDA

IPC: H03D7/14

CPC classification number: H03D7/1458 ,  H01L29/78648

Abstract: A novel semiconductor device is provided. The semiconductor device includes a mixer circuit and a bias circuit. The mixer circuit includes a voltage-to-current conversion portion, a current switch portion, and a current-to-voltage conversion portion. The bias circuit includes a bias supply portion and a first transistor. The voltage-to-current conversion portion includes a second transistor and a third transistor. The bias supply portion has a function of outputting a bias voltage to be supplied to a gate of the second transistor and a gate of the third transistor. One of a source and a drain of the first transistor is electrically connected to the gate of the second transistor and the gate of the third transistor. The first transistor is turned off when the bias voltage is supplied, and the first transistor is turned on when the supply of the bias voltage is stopped.