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公开(公告)号：US09128511B2
公开(公告)日：2015-09-08
申请号：US13709991
申请日：2012-12-10
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Jae-Min Jang
IPC: G06F3/00 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C11/4093 , G11C11/4096
CPC classification number: G06F3/00 , G11C7/1012 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.
Abstract translation: 半导体器件包括：特征码存储单元，被配置为存储通过给定焊盘输入的信号传送特性信息，并输出与信号传送特性信息相对应的控制代码;以及特性反射单元，被配置为将信号传送特性信息反映在输入 响应于控制代码通过给定焊盘的信号输入，并输出反射的输入信号。
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公开(公告)号：US09018991B2
公开(公告)日：2015-04-28
申请号：US14106817
申请日：2013-12-15
Inventor： Hae-Rang Choi , Yong-Ju Kim , Oh-Kyong Kwon , Kang-Sub Kwak , Jun-Yong Song , Hyeon-Cheon Seol
CPC classification number: H03L7/0807 , H04L7/0337 , H04L7/044
Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.
Abstract translation: 数据恢复电路可以包括适于使用数据时钟和边沿时钟对包括边缘数据的源数据进行采样的数据采样单元，适合于从数据采样单元输出的采样数据中提取边缘数据的数据提取单元，控制信号 适用于响应于边缘数据产生相位控制信号的多时钟单元，以及适于根据相位控制信号控制数据时钟和边沿时钟的相位的多时钟控制单元。
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公开(公告)号：US09225316B2
公开(公告)日：2015-12-29
申请号：US14668488
申请日：2015-03-25
Applicant: SK hynix Inc.
Inventor： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
CPC classification number: H03K3/017 , H03K5/1565
Abstract: A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
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公开(公告)号：US08461878B2
公开(公告)日：2013-06-11
申请号：US13680239
申请日：2012-11-19
Applicant: SK Hynix Inc.
Inventor： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC: H03K5/153
CPC classification number: H03K5/153
Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。
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公开(公告)号：US10256823B2
公开(公告)日：2019-04-09
申请号：US16106658
申请日：2018-08-21
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Shin-Deok Kang
Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.
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Patent Agency Ranking
公开(公告)号：US10255966B2
公开(公告)日：2019-04-09
申请号：US15641844
申请日：2017-07-05
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi
IPC: G11C11/4093 , G11C29/12 , G11C11/4091 , G11C11/406 , G11C11/408 , G11C11/4094 , G11C29/18 , G11C29/50
Abstract: A memory device includes a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell coupled to a corresponding word line among the plurality of word lines and a corresponding bit line among the plurality of bit lines; and a control block suitable for controlling at least two word lines among the plurality of word lines to be activated together, and determining whether or not a weak cell exists, based on a voltage of a bit line corresponding to the activated word lines.
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公开(公告)号：US09490853B2
公开(公告)日：2016-11-08
申请号：US14856409
申请日：2015-09-16
Inventor： Kang-Sub Kwak , Jong-Hyun Ra , Oh-Kyong Kwon , Hae-Rang Choi , Yong-Ju Kim
Abstract: A data transmitter may include a transmitter circuit and a calibration controller. The transmitter circuit is configured to be coupled to a receiver through a channel, and configured to provide an output signal to the channel based on an input signal and adjust an output impedance value according to a bias signal. The calibration controller is configured to adjust the bias signal by comparing the output signal of the transmitter circuit to a reference signal during a calibration operation.
Abstract translation: 数据发射机可以包括发射机电路和校准控制器。 发射机电路被配置为通过信道耦合到接收机，并且被配置为基于输入信号向信道提供输出信号，并根据偏置信号调整输出阻抗值。 校准控制器被配置为通过在校准操作期间将发射机电路的输出信号与参考信号进行比较来调整偏置信号。
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18.发明授权公开(公告)号：US08866526B2
公开(公告)日：2014-10-21
申请号：US14133063
申请日：2013-12-18
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim
CPC classification number: H03K5/1565 , H03K21/38
Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
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公开(公告)号：US08686768B2
公开(公告)日：2014-04-01
申请号：US13844865
申请日：2013-03-16
Applicant: SK hynix Inc.
Inventor： Hae-Rang Choi , Yong-Ju Kim , Jae-Min Jang
IPC: H03L7/06
Abstract: A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
Abstract translation: 锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测 结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。
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公开(公告)号：US20130076401A1
公开(公告)日：2013-03-28
申请号：US13680239
申请日：2012-11-19
Applicant: SK HYNIX INC.
Inventor： Ji-Wang Lee , Yong-Ju Kim , Sung-Woo Han , Hee-Woong Song , Ic-Su Oh , Hyung-Soo Kim , Tae-Jin Hwang , Hae-Rang Choi , Jae-Min Jang , Chang-Kun Park
IPC: H03K5/153
CPC classification number: H03K5/153
Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
Abstract translation: 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。
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