公开(公告)号：US20180024186A1

公开(公告)日：2018-01-25

申请号：US15546252

申请日：2016-01-19

Applicant: Soitec ,  UNIVERSITE CATHOLIQUE DU LOUVAIN

Inventor： Cédric Malaquin ,  Jean-Pierre Raskin ,  Eric Desbonnets

IPC: G01R31/28 ,  G01R29/12 ,  G01R29/08 ,  G01R31/26

CPC classification number: G01R31/2822 ,  G01R29/0878 ,  G01R29/12 ,  G01R31/2648 ,  G01R31/2831 ,  G01R31/2887 ,  G01R31/2889

Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.

公开(公告)号：US20240397825A1

公开(公告)日：2024-11-28

申请号：US18790903

申请日：2024-07-31

Applicant: Soitec

Inventor： Oleg Kononchuk ,  Eric Butaud ,  Eric Desbonnets

IPC: H10N30/072 ,  H03H3/02 ,  H03H9/00 ,  H03H9/02

Abstract: The disclosure relates to a hybrid structure for a surface-acoustic-wave device comprising a useful layer of piezoelectric material joined to a carrier substrate having a thermal expansion coefficient lower than that of the useful layer; the hybrid structure comprising an intermediate layer located between the useful layer and the carrier substrate, the intermediate layer being a structured layer formed from at least two different materials comprising a plurality of periodic motifs in the plane of the intermediate layer.

公开(公告)号：US11923239B2

公开(公告)日：2024-03-05

申请号：US17663898

申请日：2022-05-18

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L21/76283 ,  H01L21/02002 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/0649 ,  H01L29/78603 ,  H01L21/76264

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.

公开(公告)号：USRE49365E1

公开(公告)日：2023-01-10

申请号：US16920274

申请日：2020-07-02

Applicant: Soitec

Inventor： Oleg Kononchuk ,  William Van Den Daele ,  Eric Desbonnets

IPC: H03H3/02 ,  H03H3/08 ,  H01L23/06 ,  H01L41/04 ,  H01L21/306 ,  H01L21/762 ,  H01L23/66 ,  H01L21/322

Abstract: A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; a mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.

公开(公告)号：US20220368036A1

公开(公告)日：2022-11-17

申请号：US17816599

申请日：2022-08-01

Applicant: Soitec

Inventor： Eric Desbonnets ,  Bernard Aspar

IPC: H01Q23/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786 ,  H01Q1/22

Abstract: A structure for radiofrequency applications includes a high-resistivity support substrate having a front face defining a main plane, a charge-trapping layer disposed on the front face of the support substrate, a first dielectric layer disposed on the charge-trapping layer, an active layer disposed on the first dielectric layer, at least one buried electrode disposed above or in the charge-trapping layer. The buried electrode comprises a conductive layer and a second dielectric layer.

公开(公告)号：US20220076993A1

公开(公告)日：2022-03-10

申请号：US17418117

申请日：2019-12-23

Applicant: Soitec

Inventor： Yvan Morandini ,  Walter Schwarzenbach ,  Frédéric Allibert ,  Eric Desbonnets ,  Bich-Yen Nguyen

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/322 ,  H01L27/12 ,  H01L29/06

Abstract: The present disclosure relates to a multilayer semiconductor-on-insulator structure, comprising, successively from a rear face toward a front face of the structure: a semiconductor carrier substrate with high electrical resistivity, whose electrical resistivity is between 500 Ω·cm and 30 kΩ·cm, a first electrically insulating layer, an intermediate layer, a second electrically insulating layer, which has a thickness less than that of the first electrically insulating layer, an active semiconductor layer, the multilayer structure comprises: at least one FD-SOI region, in which the intermediate layer is an intermediate first semiconductor layer, at least one RF-SOI region, adjacent to the FD-SOI region, in which the intermediate layer is a third electrically insulating layer, the RF-SOI region comprising at least one radiofrequency component plumb with the third electrically insulating layer.

公开(公告)号：US11043756B2

公开(公告)日：2021-06-22

申请号：US16480249

申请日：2018-01-29

Applicant: Soitec

Inventor： Eric Desbonnets ,  Bernard Aspar

IPC: H01Q23/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/786 ,  H01Q1/22

Abstract: A structure for radiofrequency applications includes a high-resistivity support substrate having a front face defining a main plane, a charge-trapping layer disposed on the front face of the support substrate, a first dielectric layer disposed on the charge-trapping layer, an active layer disposed on the first dielectric layer, at least one buried electrode disposed above or in the charge-trapping layer. The buried electrode comprises a conductive layer and a second dielectric layer.

公开(公告)号：US20200169222A1

公开(公告)日：2020-05-28

申请号：US16614732

申请日：2018-05-23

Applicant: Soitec

Inventor： Marcel Broekaart ,  Frederic Allibert ,  Eric Desbonnets ,  Jean-Pierre Raskin ,  Martin Rack

IPC: H03C7/00 ,  H01L23/66

Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.

公开(公告)号：US20170221839A1

公开(公告)日：2017-08-03

申请号：US15500721

申请日：2015-07-03

Applicant: Soitec

Inventor： Oleg Kononchuk ,  William Van Den Daele ,  Eric Desbonnets

IPC: H01L23/66 ,  H01L41/04

CPC classification number: H01L23/66 ,  H01L21/306 ,  H01L21/76251 ,  H01L41/042 ,  H03H3/02 ,  H03H3/08

Abstract: A structure for radiofrequency applications includes: a support substrate of high-resistivity silicon comprising a lower part and an upper part having undergone a p-type doping to a depth D; mesoporous trapping layer of silicon formed in the doped upper part of the support substrate. The depth D is less than 1 micron and the trapping layer has a porosity rate of between 20% and 60%.

公开(公告)号：US11367650B2

公开(公告)日：2022-06-21

申请号：US17109978

申请日：2020-12-02

Applicant: Soitec

Inventor： Eric Desbonnets ,  Ionut Radu ,  Oleg Kononchuk ,  Jean-Pierre Raskin

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02 ,  H01L29/786 ,  H01L29/06

Abstract: Substrates for microelectronic radiofrequency devices may include a substrate comprising a semiconductor material. Trenches may be located in an upper surface of the substrate, at least some of the trenches including a filler material located within the respective trench. A resistivity of the filler material may be 10 kOhms·cm or greater. A piezoelectric material may be located on or above the upper surface of the substrate. Methods of making substrates for microelectronic radiofrequency devices may involve forming trenches in an upper surface of a substrate including a semiconductor material. A filler material may be placed in at least some of the trenches, and a piezoelectric material may be placed on or above the upper surface of the substrate.