公开(公告)号：US11784104B2

公开(公告)日：2023-10-10

申请号：US17491189

申请日：2021-09-30

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Olivier Ory ,  Romain Jaillet

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/78 ,  H01L29/861

CPC classification number: H01L23/3114 ,  H01L21/561 ,  H01L21/78 ,  H01L29/861

Abstract: The invention concerns a device comprising a support, an electrically-conductive layer covering the support, a semiconductor substrate on the conductive layer, and an insulating casing.

公开(公告)号：US11296071B2

公开(公告)日：2022-04-05

申请号：US16834499

申请日：2020-03-30

Applicant: STMicroelectronics (Tours) SAS

Inventor： Eric Laconde ,  Olivier Ory

IPC: H01L27/02 ,  H01L27/08

Abstract: A device of protection against electrostatic discharges is formed in a semiconductor substrate of a first conductivity type that is coated with a semiconductor layer of a second conductivity type. A buried region of the second conductivity type is positioned at an interface between the semiconductor substrate and the semiconductor layer. First and second wells of the first conductivity type are formed in the semiconductor layer and a region of the second conductivity type is formed in the second well. A stop channel region of the second conductivity type is provided in the semiconductor layer to laterally separating the first well from the second well, where no contact is present between this stop channel region and either of the first and second wells.

公开(公告)号：US20170084482A1

公开(公告)日：2017-03-23

申请号：US15367364

申请日：2016-12-02

Applicant: STMicroelectronics (Tours) SAS

Inventor： Olivier Ory

IPC: H01L21/768 ,  H01L23/538 ,  H01L21/3065

CPC classification number: H01L21/76843 ,  H01L21/302 ,  H01L21/3043 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76867 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0657 ,  H01L29/16 ,  H01L2224/02311 ,  H01L2224/02371 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/94 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2924/00014

Abstract: A surface-mount chip is formed by a silicon substrate having a front surface and a side. The chip includes a metallization intended to be soldered to an external device. The metallization has a first portion covering at least a portion of the front surface of the substrate and a second portion covering at least a portion of the side of the substrate. A porous silicon region is included in the substrate to separating the second portion of the metallization from the rest of the substrate.

公开(公告)号：US20140035132A1

公开(公告)日：2014-02-06

申请号：US13955325

申请日：2013-07-31

Applicant: Universite Francois Rabelais ,  STMicroelectronics (Tours) SAS

Inventor： Olivier Ory ,  Cedric Le Coq

IPC: H01L23/00

CPC classification number: H01L24/01 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/1403 ,  H01L2224/14051

Abstract: A surface mount chip including, on the side of a surface, first and second pads of connection to an external device, wherein, in top view, the first pad has an elongated general shape, and the second pad is a point-shaped pad which is not aligned with the first pad.

Abstract translation: 一种表面贴装芯片，其在表面侧包括与外部装置连接的第一和第二焊盘，其中，在顶视图中，第一焊盘具有细长的总体形状，第二焊盘是点状焊盘， 不与第一个垫对齐。