公开(公告)号：US20150365080A1

公开(公告)日：2015-12-17

申请号：US14304357

申请日：2014-06-13

Applicant: STMicroelectronics International N.V.

Inventor： Shishir Kumar ,  Tanmoy Roy

IPC: H03K5/01 ,  G11C8/18

CPC classification number: H03K5/01 ,  G11C7/222 ,  G11C8/18

Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

Abstract translation: 根据实施例，一种产生时钟脉冲的方法包括在使能信号有效时在时钟输入端处接收前沿，在时钟输出端基于接收到的前沿产生时钟输出的边沿，锁存 对应于时钟输出端的逻辑值，防止在逻辑值被锁存之后时钟输入的变化影响锁存的逻辑值，在第一延迟时间之后复位锁存的逻辑值，并保持复位逻辑值直到 在时钟输入端接收第二个边沿。 时钟输入端的第二个边沿与时钟输入端的前沿匹配。

公开(公告)号：US12243584B2

公开(公告)日：2025-03-04

申请号：US18167580

申请日：2023-02-10

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Tanmoy Roy ,  Nitin Chawla

IPC: G11C11/41 ,  G11C11/419 ,  H10B10/00

Abstract: An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.

公开(公告)号：US11742045B2

公开(公告)日：2023-08-29

申请号：US17222119

申请日：2021-04-05

Applicant: STMicroelectronics International N.V.

Inventor： Rohit Bhasin ,  Shishir Kumar ,  Tanmoy Roy ,  Deepak Kumar Bihani

IPC: G11C29/38 ,  G11C29/14

CPC classification number: G11C29/38 ,  G11C29/14

Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

公开(公告)号：US11605424B2

公开(公告)日：2023-03-14

申请号：US17375945

申请日：2021-07-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anuj Grover ,  Tanmoy Roy ,  Nitin Chawla

IPC: G11C11/41 ,  G11C11/419 ,  H01L27/11

Abstract: An in-memory compute (IMC) device includes a compute array having a first plurality of cells. The compute array is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. Each cell of the first plurality of cells is identifiable by its corresponding row and column. The IMC device also includes a plurality of computation engines and a plurality of bias engines. Each computation engine is respectively formed in a different one of a second plurality of cells, wherein the second plurality of cells is formed from cells of the first plurality. Each computation engine is formed at a respective row and column intersection. Each bias engine of the plurality of bias engines is arranged to computationally combine an output from at least one of the plurality of computation engines with a respective bias value.

公开(公告)号：US11335397B2

公开(公告)日：2022-05-17

申请号：US16994488

申请日：2020-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Tanmoy Roy

IPC: G11C16/04 ,  G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

公开(公告)号：US10283191B1

公开(公告)日：2019-05-07

申请号：US15917227

申请日：2018-03-09

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Pathak ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/00 ,  G11C11/412 ,  G11C7/14 ,  G11C11/419

Abstract: Disclosed herein is a memory circuit including a dummy word line driver driving a dummy word line, dummy memory cells coupled to a dummy bit line and a dummy complementary bit line, and a transmission gate coupled to the dummy word line to pass a word line signal from the dummy word line driver to an input of the dummy memory cells. A transistor is coupled to the dummy word line between the transmission gate and a pair of pass gates of a given one of the dummy memory cells closest to the transmission gate along the dummy word line. A reset signal output is coupled to the dummy complementary bit line. The transistor serves to lower a voltage on the dummy word line, and a reset signal indicating an end of a measured dummy cycle is generated at the reset signal output.

公开(公告)号：US11889675B2

公开(公告)日：2024-01-30

申请号：US18052514

申请日：2022-11-03

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar Sharma ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C7/10 ,  H10B10/00 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

CPC classification number: H10B10/12 ,  G11C5/063 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L27/0207

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US11798615B2

公开(公告)日：2023-10-24

申请号：US17721956

申请日：2022-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Tanmoy Roy

IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4085 ,  G11C5/025 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

公开(公告)号：US11474788B2

公开(公告)日：2022-10-18

申请号：US16890870

申请日：2020-06-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin Chawla ,  Tanmoy Roy ,  Anuj Grover ,  Giuseppe Desoli

IPC: G06F7/57 ,  G06F3/06 ,  G06N3/063

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.

公开(公告)号：US10277207B1

公开(公告)日：2019-04-30

申请号：US15892308

申请日：2018-02-08

Applicant: STMicroelectronics International N.V.

Inventor： Alok Kumar Tripathi ,  Amit Verma ,  Anuj Grover ,  Deepak Kumar Bihani ,  Tanmoy Roy ,  Tanuj Agrawal

IPC: H03K3/00 ,  H03K3/3562 ,  G11C11/412

Abstract: The present disclosure is directed to a master-slave flip-flop memory circuit having a partial pass gate transistor at the input of the master latch. The partial pass gate transistor includes a pull-up clock enabled transistor for selectively coupling a high output of a test switch to the input of the master latch. The input of the master latch is also directly coupled to a low output of the test switch around the partial pass gate. In addition, a revised circuit layout is provided in which the master latch has three inverters. A first inverter is coupled to the input of the master latch. Second and third inverters are coupled to an output of the first inverter, with the second inverter having an output coupled to the input of the first inverter, and the third inverter having an output coupled to an output of the master latch. The first and second inverters are clock enabled, and the third inverter is reset enabled.