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    High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor
    13.
    发明授权
    High-voltage capacitor, system including the capacitor and method for manufacturing the capacitor 有权

    公开(公告)号：US10916622B2

    公开(公告)日：2021-02-09

    申请号：US16144168

    申请日：2018-09-27

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Davide Giuseppe Patti ,  Giuseppina Valvo ,  DelfoNunziato Sanfilippo

    IPC: H01L49/02 ,  H01L23/522

    Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.

    Integrated vacuum microelectronic device and fabrication method thereof
    15.
    发明授权
    Integrated vacuum microelectronic device and fabrication method thereof 有权
    集成真空微电子器件及其制造方法

    公开(公告)号：US09508520B2

    公开(公告)日：2016-11-29

    申请号：US14290583

    申请日：2014-05-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Davide Giuseppe Patti

    IPC: H01J1/304 ,  H01J9/02 ,  H01J21/10

    CPC classification number: H01J1/3044 ,  H01J9/025 ,  H01J9/027 ,  H01J21/105

    Abstract: An integrated vacuum microelectronic device comprises: a highly doped semiconductor substrate, at least one insulating layer) placed above said doped semiconductor substrate, a vacuum aperture formed within said at least one insulating layer and extending to the highly doped semiconductor substrate, a first metal layer acting as a cathode, a second metal layer placed under said highly doped semiconductor substrate and acting as an anode. The first metal layer is placed adjacent to the upper edge of the vacuum aperture and the vacuum aperture has a width dimension such as the first metal layer remains suspended over the vacuum aperture.

    Abstract translation: 集成的真空微电子器件包括：放置在所述掺杂半导体衬底之上的高掺杂半导体衬底，至少一个绝缘层），形成在所述至少一个绝缘层内并延伸到高掺杂半导体衬底的真空孔，第一金属层 充当阴极，位于所述高掺杂半导体衬底下方并用作阳极的第二金属层。 第一金属层被放置成与真空孔的上边缘相邻，并且真空孔具有诸如第一金属层保持悬挂在真空孔上的宽度尺寸。

    INTEGRATED VERTICAL TRENCH MOS TRANSISTOR
    16.
    发明申请
    INTEGRATED VERTICAL TRENCH MOS TRANSISTOR 审中-公开
    集成垂直三通MOS晶体管

    公开(公告)号：US20160087080A1

    公开(公告)日：2016-03-24

    申请号：US14949528

    申请日：2015-11-23

    Applicant: STMicroelectronics S.R.L.

    Inventor： Antonio Giuseppe Grimaldi ,  Davide Giuseppe Patti ,  Monica Miccichè ,  Salvatore Liotta ,  Angela Longhitano

    IPC: H01L29/66 ,  H01L29/423

    CPC classification number: H01L29/66666 ,  H01L27/0629 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/6609 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861

    Abstract: A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip.

    Abstract translation: 第一导电类型的半导体材料中的VTMOS晶体管包括第二导电类型的体区和第一类导电性的源区。 栅极区域通过主体区域延伸到主表面并与半导体材料绝缘。 延伸到主表面上的栅极区域的区域与栅极区域的其余部分绝缘。 第一导电类型的阳极区域形成在所述绝缘区域中，并且第二导电类型的阴极区域形成为与阳极区域接触的所述绝缘区域; 阳极区域和阴极区域限定与芯片电绝缘的热二极管。

    INTEGRATED VACUUM MICROELECTRONIC DEVICE AND FABRICATION METHOD THEREOF
    17.
    发明申请
    INTEGRATED VACUUM MICROELECTRONIC DEVICE AND FABRICATION METHOD THEREOF 有权
    集成真空微电子器件及其制造方法

    公开(公告)号：US20140353576A1

    公开(公告)日：2014-12-04

    申请号：US14290583

    申请日：2014-05-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Davide Giuseppe Patti

    IPC: H01J1/304

    CPC classification number: H01J1/3044 ,  H01J9/025 ,  H01J9/027 ,  H01J21/105

    Abstract: An integrated vacuum microelectronic device comprises: a highly doped semiconductor substrate, at least one insulating layer) placed above said doped semiconductor substrate, a vacuum aperture formed within said at least one insulating layer and extending to the highly doped semiconductor substrate, a first metal layer acting as a cathode, a second metal layer placed under said highly doped semiconductor substrate and acting as an anode. The first metal layer is placed adjacent to the upper edge of the vacuum aperture and the vacuum aperture has a width dimension such as the first metal layer remains suspended over the vacuum aperture.

    Abstract translation: 集成的真空微电子器件包括：放置在所述掺杂半导体衬底之上的高掺杂半导体衬底，至少一个绝缘层），形成在所述至少一个绝缘层内并延伸到高掺杂半导体衬底的真空孔，第一金属层 充当阴极，位于所述高掺杂半导体衬底下方并用作阳极的第二金属层。 第一金属层被放置成与真空孔的上边缘相邻，并且真空孔具有诸如第一金属层保持悬挂在真空孔上的宽度尺寸。

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