公开(公告)号：US20150296018A1

公开(公告)日：2015-10-15

申请号：US14659159

申请日：2015-03-16

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Daniele Mangano

IPC: H04L29/08 ,  H04L12/721

CPC classification number: H04L67/1097 ,  G06F13/1626 ,  G06F13/4022 ,  G06F2213/0038 ,  H04L45/72

Abstract: A system to manage out-of-order traffic in an interconnect network has initiators that provide requests through the interconnect network to memory resource targets and provide responses back through the interconnect network. The system includes components upstream the interconnect network to perform response re-ordering, which include memory to store responses from the interconnect network and a memory map controller to store the responses on a set of logical circular buffers. Each logical circular buffer corresponds to an initiator. The memory map controller computes an offset address for each buffer and stores an offset address of a given request received on a request path. The controller computes an absolute write memory address where responses are written in the memory, the response corresponding to the given request based on the given request offset address. The memory map controller also performs an order-controlled parallel read of the logical circular buffers and routes the data read from the memory to the corresponding initiator.

Abstract translation: 用于管理互连网络中的乱序流量的系统具有通过互连网络向存储器资源目标提供请求并且通过互连网络提供响应的启动器。 该系统包括互连网络上游的组件以执行响应重新排序，其包括用于存储来自互连网络的响应的存储器和存储映射控制器以将响应存储在一组逻辑循环缓冲器上。 每个逻辑循环缓冲区对应于启动器。 存储器映射控制器计算每个缓冲器的偏移地址，并存储在请求路径上接收的给定请求的偏移地址。 控制器计算绝对写存储器地址，其中响应被写入存储器中，该响应对应于给定的请求，基于给定的请求偏移地址。 存储器映射控制器还执行逻辑循环缓冲器的顺序控制的并行读取，并将从存储器读取的数据路由到相应的启动器。

公开(公告)号：US20240160598A1

公开(公告)日：2024-05-16

申请号：US18503744

申请日：2023-11-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Mirko Dondini ,  Calogero Andrea Trecarichi ,  Fred Rennig

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/40

Abstract: An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode. During the initialization mode, the hardware host circuit stores the CD1 to the configuration and status registers and the CD2 to the volatile memory.

公开(公告)号：US11543842B2

公开(公告)日：2023-01-03

申请号：US16803942

申请日：2020-02-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mirko Dondini ,  Daniele Mangano ,  Riccardo Condorelli

IPC: G05F1/00 ,  G05F1/575 ,  G05B19/042 ,  G06F13/40 ,  H03B5/32 ,  H03K19/17736

Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.

公开(公告)号：US09959226B2

公开(公告)日：2018-05-01

申请号：US14841522

申请日：2015-08-31

Applicant: STMicroelectronics S.R.L.

Inventor： Daniele Mangano ,  Mirko Dondini ,  Salvatore Pisasale

IPC: G06F13/28 ,  G06F13/40 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/067 ,  G06F13/4059 ,  G06F2213/0038

Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.

公开(公告)号：US09471521B2

公开(公告)日：2016-10-18

申请号：US14278403

申请日：2014-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Daniele Mangano ,  Giuseppe Falconeri

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.

Abstract translation: 通信系统被布置为将多个传输电路与互连网络接口。 每个传输电路产生读请求和/或写请求。 通信系统包括独立于互连网络的通信协议操作的第一电路。 特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求 和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。 通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。

公开(公告)号：US12038471B2

公开(公告)日：2024-07-16

申请号：US17406962

申请日：2021-08-19

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Roberto Crisafulli ,  Calogero Andrea Trecarichi ,  Vincenzo Randazzo

IPC: G01R31/28

CPC classification number: G01R31/2843 ,  G01R31/2839

Abstract: An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.

公开(公告)号：US11764773B2

公开(公告)日：2023-09-19

申请号：US17545719

申请日：2021-12-08

Applicant: STMicroelectronics S.r.l.

Inventor： Enrico Castro ,  Giovanni Susinna ,  Vincenzo Randazzo ,  Mirko Dondini ,  Calogero Andrea Trecarichi

IPC: H03K17/082 ,  H02H9/02

CPC classification number: H03K17/0822 ,  H02H9/02

Abstract: Current absorption management for an electronic fuse coupled between an electrical supply source node and an electrical load node selectively controls a high current electronic switch and a low current electronic switch coupled in parallel between the electrical supply source node and the electrical load node. The high current and low current electronic switches are alternatively actuated: in a first mode where the high current electronic switch is turned on and the low current electronic switch is turned off, and in a second mode where the high current electronic switch is turned off and the low current electronic switch is turned on. Change to the second mode may be made in response to a standby state or a sensing of a lower current in the electrical load. Conversely, change to the first mode may be made in response to a sensing of a higher current in the electrical load.

公开(公告)号：US20200278393A1

公开(公告)日：2020-09-03

申请号：US16791020

申请日：2020-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko Dondini ,  Daniele Mangano ,  Salvatore Pisasale

IPC: G01R31/3185 ,  G01R31/319 ,  G01R29/027 ,  G06F1/08 ,  G06F1/12 ,  G06F13/24

Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.

公开(公告)号：US20150370734A1

公开(公告)日：2015-12-24

申请号：US14841522

申请日：2015-08-31

Applicant: STMicroelectronics S.R.L.

Inventor： Daniele Mangano ,  Mirko Dondini ,  Salvatore Pisasale

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/067 ,  G06F13/4059 ,  G06F2213/0038

Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. In the case where the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, in the case where the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.

Abstract translation: 通信接口将传输电路与互连网络耦合。 发送电路请求发送预定量的数据。 通信接口从发送电路接收数据段，将数据段存储在存储器中，并且验证存储器是否包含预定量的数据。 在存储器包含预定量的数据的情况下，通信接口开始存储在存储器中的数据的发送。 或者，在存储器包含小于预定数据量的数据量的情况下，通信接口确定从上述发送电路接收到从发送请求或第一基准开始经过的时间的参数， 并验证所经过的时间是否超过时间阈值。 在经过时间超过时间阈值的情况下，通信接口开始存储在存储器中的数据的发送。