PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD

    公开(公告)号:US20240160598A1

    公开(公告)日:2024-05-16

    申请号:US18503744

    申请日:2023-11-07

    CPC classification number: G06F13/4282 G06F2213/40

    Abstract: An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode. During the initialization mode, the hardware host circuit stores the CD1 to the configuration and status registers and the CD2 to the volatile memory.

    Electronic device and corresponding self-test method

    公开(公告)号:US12038471B2

    公开(公告)日:2024-07-16

    申请号:US17406962

    申请日:2021-08-19

    CPC classification number: G01R31/2843 G01R31/2839

    Abstract: An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.

    Current absorption management circuit, corresponding system and method

    公开(公告)号:US11764773B2

    公开(公告)日:2023-09-19

    申请号:US17545719

    申请日:2021-12-08

    CPC classification number: H03K17/0822 H02H9/02

    Abstract: Current absorption management for an electronic fuse coupled between an electrical supply source node and an electrical load node selectively controls a high current electronic switch and a low current electronic switch coupled in parallel between the electrical supply source node and the electrical load node. The high current and low current electronic switches are alternatively actuated: in a first mode where the high current electronic switch is turned on and the low current electronic switch is turned off, and in a second mode where the high current electronic switch is turned off and the low current electronic switch is turned on. Change to the second mode may be made in response to a standby state or a sensing of a lower current in the electrical load. Conversely, change to the first mode may be made in response to a sensing of a higher current in the electrical load.

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