公开(公告)号：US20170186759A1

公开(公告)日：2017-06-29

申请号：US15133394

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/115 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L49/02

CPC classification number: H01L27/11546 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/823468 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11541 ,  H01L28/00 ,  H01L28/60 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US20160380030A1

公开(公告)日：2016-12-29

申请号：US14970347

申请日：2015-12-15

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  G11C13/0004 ,  G11C2213/79 ,  G11C2213/82 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract translation: 本公开涉及一种形成在晶片中的存储单元，其包括被第一绝缘层覆盖的半导体衬底，绝缘层被由半导体制成的有源层覆盖，所述存储单元包括具有控制栅极和第一绝缘层的选择晶体管 所述导电端子连接到可变电阻元件，所述栅极形成在所述有源层上并具有被第二绝缘层覆盖的侧面，所述可变电阻元件由可变电阻材料层形成，所述可变电阻材料层沉积在侧向 有源层的沿着栅极的侧面通过有源层形成的第一沟槽的侧面，沟槽导体形成在第一沟槽中，抵抗可变电阻材料层的侧面。

公开(公告)号：US20160276451A1

公开(公告)日：2016-09-22

申请号：US14930150

申请日：2015-11-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Dominique Golanski ,  Gregory Bidal ,  Simon Jeannot

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/788 ,  H01L29/66 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L27/12 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7838 ,  H01L29/7881

Abstract: An integrated circuit includes a first zone for a first transistor and a second zone for a second transistor. The transistors are supported by a substrate of the silicon-on-insulator type that includes a semiconductor film on a buried insulating layer on a carrier substrate. In the second zone, the semiconductor film has been removed. The second transistor in the second zone includes a gate-dielectric region resting on the carrier substrate that is formed by a portion of the buried insulating layer). The first transistor in the first zone includes a gate-dielectric region formed by a dielectric layer on the semiconductor film.

Abstract translation: 集成电路包括用于第一晶体管的第一区和用于第二晶体管的第二区。 晶体管由绝缘体上的类型的衬底支撑，其中包括在载体衬底上的掩埋绝缘层上的半导体膜。 在第二区域中，已经去除了半导体膜。 第二区域中的第二晶体管包括搁置在由掩埋绝缘层的一部分形成的载体衬底上的栅极介电区域）。 第一区域中的第一晶体管包括由半导体膜上的电介质层形成的栅介电区域。

公开(公告)号：US11495609B2

公开(公告)日：2022-11-08

申请号：US17092551

申请日：2020-11-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/11541

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US10283563B2

公开(公告)日：2019-05-07

申请号：US15694463

申请日：2017-09-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Philippe Boivin ,  Simon Jeannot

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

公开(公告)号：US09978764B2

公开(公告)日：2018-05-22

申请号：US15133394

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto Piazza ,  Sebastien Lagrasta ,  Raul Andres Bianchi ,  Simon Jeannot

IPC: H01L27/115 ,  H01L27/11546 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L49/02 ,  H01L29/49 ,  H01L29/66 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/11541

CPC classification number: H01L27/11546 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/28273 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/823468 ,  H01L27/0629 ,  H01L27/11521 ,  H01L27/11541 ,  H01L28/00 ,  H01L28/60 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.