公开(公告)号：US20200035304A1

公开(公告)日：2020-01-30

申请号：US16048524

申请日：2018-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Roberto SIMOLA

IPC: G11C16/04 ,  H01L29/423 ,  H01L27/11517

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

公开(公告)号：US20230402102A1

公开(公告)日：2023-12-14

申请号：US18324850

申请日：2023-05-26

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francois TAILLIET

IPC: G11C16/12 ,  G11C16/30 ,  G11C16/08

CPC classification number: G11C16/12 ,  G11C16/30 ,  G11C16/08

Abstract: The latch device includes an RS type latch flip-flop capable of being supplied between a first supply voltage and a second supply voltage which is lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output connected to the output terminal. A control module positions the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage then, the latch flip-flop being positioned, confers the high voltage on the first supply voltage and the low voltage on the second supply voltage and outputs and maintains the high voltage or the low voltage on the flip-flop output while avoiding outputting a prohibited logic state at the two flip-flop inputs.

公开(公告)号：US20230299127A1

公开(公告)日：2023-09-21

申请号：US18180025

申请日：2023-03-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Loic WELTER ,  Maria-Paz DUMITRESCU ,  Roberto SIMOLA

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L21/28 ,  H01L29/788 ,  H01L21/762 ,  H10B41/10 ,  H10B41/35

CPC classification number: H01L29/0607 ,  H01L29/7835 ,  H01L27/0922 ,  H01L29/6659 ,  H01L29/402 ,  H01L29/42324 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883 ,  H01L21/76224 ,  H10B41/10 ,  H10B41/35

Abstract: The integrated circuit comprises at least one transistor including a separate gate structure and field plate, disposed on a front face of a semiconductor substrate, and a doped conduction region in the semiconductor substrate located plumb with an edge of the gate structure and plumb with an edge of the field plate.

公开(公告)号：US20220123119A1

公开(公告)日：2022-04-21

申请号：US17504198

申请日：2021-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Philippe BOIVIN ,  Francois TAILLIET ,  Roberto SIMOLA

IPC: H01L29/423 ,  H01L27/11524 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.

公开(公告)号：US20220107356A1

公开(公告)日：2022-04-07

申请号：US17468377

申请日：2021-09-07

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Francois TAILLIET

IPC: G01R31/28 ,  G01R1/067

Abstract: A test circuit and a method for testing an integrated circuit are provided. The integrated circuit includes a test circuit. The test circuit includes a conductive track extending over at least a portion of the periphery of the integrated circuit, at least one component and an activation circuit adapted to deviating an input data signal into the conductive track during a test mode, and to transmitting the input data signal to the at least one component during a normal operating mode.

公开(公告)号：US20210280228A1

公开(公告)日：2021-09-09

申请号：US17188569

申请日：2021-03-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Beatrice BROCHIER ,  Sylvain FIDELIS

IPC: G11C7/22 ,  G11C7/10

Abstract: A contactless transponder includes a non-volatile static random access memory including memory points. Each memory point is formed by a volatile memory cell and a non-volatile memory cell. A protocol processing circuit receives data and stores the received data in the volatile memory cells of the memory. A write processing circuit is configured, at the end of the reception and storage of the data, to record, in a single write cycle, the data from the volatile memory cells to the non-volatile memory cells of the respective memory points.

公开(公告)号：US20200327092A1

公开(公告)日：2020-10-15

申请号：US16840759

申请日：2020-04-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET

IPC: G06F13/42 ,  G06F13/12 ,  G06F9/30 ,  G06F11/07 ,  G11C7/10 ,  G11C16/34

Abstract: A method for encoding a data value to be transmitted on an SPI serial bus includes an operation to modify a status register of a memory, at least at one chosen time instant, as a function of all or part of the data value to be transmitted.

公开(公告)号：US20190057963A1

公开(公告)日：2019-02-21

申请号：US16053304

申请日：2018-08-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET

IPC: H01L27/088 ,  H01L21/762

Abstract: An electronic chip is provided that includes a plurality of first transistors electrically coupled to one another in parallel. A plurality of first isolating trenches is included in the electronic chip, and the first transistors are separated from one another by the first isolating trenches. Each of the first isolation trenches has a depth and a maximum width, and the depth depends on, or is a function of, the maximum width.