公开(公告)号：US10215782B2

公开(公告)日：2019-02-26

申请号：US15372127

申请日：2016-12-07

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Vanni Poletto ,  Riccardo Miglierina ,  Antonio Davide Leone ,  Sergio Lecce

IPC: G01R19/165 ,  G11C27/02 ,  H03F3/45 ,  G01R31/34

Abstract: A device measures the current in an inductive load using two separate current-measuring paths to detect the current in the inductive load. The inductive load is connected between first and second nodes, and the first node connected to a first voltage. The device includes first and second transistors cascaded together between the first node and a third node that is connected to a second voltage. First and second sense amplifiers measure the current in the inductive load. The first and second sense amplifiers are connected to at least one terminal of the first and second transistors. Two blocks sample and hold signals from the first and second sense amplifiers, which represent, respectively, the currents in the two separate current-measuring paths. The two currents are subtracted in a comparison node for generating an error signal that is compared with a predefined window and if outside the window a failure signal is generated.

公开(公告)号：US20180175856A1

公开(公告)日：2018-06-21

申请号：US15898931

申请日：2018-02-19

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Zella ,  Vanni Poletto ,  Mauro Foppiani

IPC: H03K17/687 ,  G05F3/26 ,  H03K17/60

CPC classification number: H03K17/6872 ,  G05F3/26 ,  H03K17/60 ,  H03K17/687

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

公开(公告)号：US20180159518A1

公开(公告)日：2018-06-07

申请号：US15634616

申请日：2017-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Vanni Poletto ,  Andrea Maino

IPC: H03K5/1532 ,  H03K7/08 ,  H02P27/08

CPC classification number: H03K5/1532 ,  H02P7/02 ,  H02P7/025 ,  H02P7/04 ,  H02P27/085 ,  H03K7/08 ,  H03K17/165 ,  H03K17/689

Abstract: A ringing peak detector module detects a ringing at the output of an inductive load driver including a bridge circuit containing high side and low side switches. A ringing peak detector receives differential feedback signals representative of the drain-source voltage of the low-side switch and detects a ringing peak of an oscillation of a current/voltage on the inductive load. A module compares said detected ringing peak with a maximum value and controls said driver by an error signal calculated as a function of the difference between said peak value and maximum value. The ringing peak detector module includes an input buffer module upstream of said peak detector circuit that shifts the differential feedback signals so a common mode of these signals is centered at a half-dynamic level of a supply voltage to provide correspondingly shifted voltages forming a shifted differential output corresponding to a steady state of the differential feedback signals.

公开(公告)号：US11996851B2

公开(公告)日：2024-05-28

申请号：US17556495

申请日：2021-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Vanni Poletto ,  Ivan Floriani

IPC: H03M3/00 ,  H02M1/096 ,  H02M3/156 ,  H03K9/08

CPC classification number: H03K9/08 ,  H02M1/096 ,  H02M3/156

Abstract: A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.

公开(公告)号：US11789046B2

公开(公告)日：2023-10-17

申请号：US17407725

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Davide Argento ,  Orazio Pennisi ,  Stefano Castorina ,  Vanni Poletto ,  Matteo Landini ,  Andrea Maino

IPC: G01R19/10 ,  H03M1/12 ,  H03M3/00 ,  B60R21/017

CPC classification number: G01R19/10 ,  B60R21/0173 ,  H03M1/124 ,  H03M3/464 ,  H03M3/494

Abstract: A system and method is provided for measuring a voltage drop at a node. In embodiments, a circuit includes an analog-to-digital converter, a current sink, and a controller. The input of the analog-to-digital converter and the input of the current sink is coupled to the node to be measured. A set point for the current sink is determined. The output of the analog-to-digital converter during the voltage drop is sampled. And a relative voltage drop value is computed by subtracting the sampled output of the analog-to-digital converter during the voltage drop from a sampled output of the analog-to-digital converter during a steady-state condition. The current sink operating at the set point during the steady-state condition and during the voltage drop.

公开(公告)号：US20230308066A1

公开(公告)日：2023-09-28

申请号：US18180595

申请日：2023-03-08

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Rogledi ,  Vanni Poletto ,  Antonio Davide Leone

IPC: H03G3/30 ,  H03F3/04

CPC classification number: H03G3/30 ,  H03F3/04 ,  H03G2201/103

Abstract: In accordance with an embodiment, a variable gain amplifier includes: a first differential transistor pair coupled to a signal input; a first current source configured to provide a first bias current to the first differential transistor pair; a pair of diodes coupled to an output of the first differential transistor pair; a second differential transistor pair having an input coupled to the pair of diodes; a second current source configured to provide a second bias current to the second differential transistor pair; and a current control circuit coupled to the first current source and the second current source.

公开(公告)号：US10571943B2

公开(公告)日：2020-02-25

申请号：US15637225

申请日：2017-06-29

Applicant: STMicroelectronics S.r.l.

Inventor： Vanni Poletto ,  Biagio Provinzano

IPC: H03K17/042 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  G05F1/575 ,  H03F3/45 ,  H03F3/50

Abstract: A (pre) driver circuit includes first and second output terminals configured to be coupled to a power transistor. A differential stage has non-inverting and inverting inputs for receiving an input voltage. The input voltage is replicated as an output voltage across the first and second output terminals as a drive signal for the power transistor. The differential stage includes a differential transconductance amplifier in a voltage follower arrangement configured to provide continuous regulation of a voltage at the first output terminal with respect to the second output terminal.

公开(公告)号：US10444264B2

公开(公告)日：2019-10-15

申请号：US16262521

申请日：2019-01-30

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Vanni Poletto ,  Riccardo Miglierina ,  Antonio Davide Leone ,  Sergio Lecce

IPC: G01R19/165 ,  G01R31/34 ,  H03F3/45 ,  G11C27/02

Abstract: A device measures the current in an inductive load using two separate current-measuring paths to detect the current in the inductive load. The inductive load is connected between first and second nodes, and the first node connected to a first voltage. The device includes first and second transistors cascaded together between the first node and a third node that is connected to a second voltage. First and second sense amplifiers measure the current in the inductive load. The first and second sense amplifiers are connected to at least one terminal of the first and second transistors. Two blocks sample and hold signals from the first and second sense amplifiers, which represent, respectively, the currents in the two separate current-measuring paths. The two currents are subtracted in a comparison node for generating an error signal that is compared with a predefined window and if outside the window a failure signal is generated.

公开(公告)号：US10374603B2

公开(公告)日：2019-08-06

申请号：US15898931

申请日：2018-02-19

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Zella ,  Vanni Poletto ,  Mauro Foppiani

IPC: H03K3/00 ,  H03K17/687 ,  G05F3/26 ,  H03K17/60

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

公开(公告)号：US10009018B1

公开(公告)日：2018-06-26

申请号：US15634616

申请日：2017-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Vanni Poletto ,  Andrea Maino

IPC: H02P6/06 ,  H03K5/1532 ,  H03K7/08 ,  H02P27/08

Abstract: A ringing peak detector module detects a ringing at the output of an inductive load driver including a bridge circuit containing high side and low side switches. A ringing peak detector receives differential feedback signals representative of the drain-source voltage of the low-side switch and detects a ringing peak of an oscillation of a current/voltage on the inductive load. A module compares said detected ringing peak with a maximum value and controls said driver by an error signal calculated as a function of the difference between said peak value and maximum value. The ringing peak detector module includes an input buffer module upstream of said peak detector circuit that shifts the differential feedback signals so a common mode of these signals is centered at a half-dynamic level of a supply voltage to provide correspondingly shifted voltages forming a shifted differential output corresponding to a steady state of the differential feedback signals.