公开(公告)号：US20180190346A1

公开(公告)日：2018-07-05

申请号：US15909261

申请日：2018-03-01

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Vinay Kumar ,  Kedar Janardan Dhori

IPC: G11C11/419 ,  G11C5/14 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C5/145 ,  G11C5/147 ,  G11C11/418

Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

公开(公告)号：US09208040B2

公开(公告)日：2015-12-08

申请号：US14266067

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Vinay Kumar ,  PraveenKumar Verma

IPC: G06F11/00 ,  G06F11/20

CPC classification number: G11C29/702 ,  G06F11/2094 ,  G06F2201/85

Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.

Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。

公开(公告)号：US20150317225A1

公开(公告)日：2015-11-05

申请号：US14266067

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Vinay Kumar ,  PraveenKumar Verma

IPC: G06F11/20

CPC classification number: G11C29/702 ,  G06F11/2094 ,  G06F2201/85

Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.

Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。

公开(公告)号：US12176025B2

公开(公告)日：2024-12-24

申请号：US17844955

申请日：2022-06-21

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Promod Kumar ,  Nitin Chawla ,  Manuj Ayodhyawasi

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

公开(公告)号：US12165698B2

公开(公告)日：2024-12-10

申请号：US17483501

申请日：2021-09-23

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan Dhori

IPC: G11C11/417 ,  G11C11/412

Abstract: A static random access memory (SRAM) device disclosed herein includes an array of SRAM cells powered between first and second voltages. A reference voltage generator generates a reference voltage that is proportional to absolute temperature, with a magnitude curve of the reference voltage being based upon a control word. A low dropout amplifier sets and maintains the second voltage as being equal to the reference voltage. Control circuitry generates the control word based upon process variation information about the SRAM device. In one instance, the control circuitry monitors a canary bit-cell and increments the control word, to thereby increase the magnitude curve of the reference voltage, until the canary bit-cell fails. In another instance, the control circuitry measures the oscillation frequency of a ring oscillator, and selects the control word based upon the measured oscillation frequency.

公开(公告)号：US11726543B2

公开(公告)日：2023-08-15

申请号：US17111373

申请日：2020-12-03

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin Chawla ,  Anuj Grover ,  Giuseppe Desoli ,  Kedar Janardan Dhori ,  Thomas Boesch ,  Promod Kumar

IPC: G06F1/3234 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/78 ,  G11C11/413 ,  G11C5/14 ,  G11C11/417 ,  G06F1/26

CPC classification number: G06F1/3275 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/7821 ,  G11C11/413

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US09940997B2

公开(公告)日：2018-04-10

申请号：US15447853

申请日：2017-03-02

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Vinay Kumar ,  Kedar Janardan Dhori

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C5/145 ,  G11C5/147 ,  G11C11/418

Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

公开(公告)号：US20170301396A1

公开(公告)日：2017-10-19

申请号：US15132680

申请日：2016-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan Dhori ,  Ashish Kumar ,  Hitesh Chawla ,  Praveen Kumar Verma

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/418

Abstract: A memory circuit includes a wordline, memory cells connected to the wordline and a wordline driver circuit including a p-channel pull-up transistor. The memory circuit further includes a read assist circuit including an n-channel pull-down transistor having a source-drain path connected between the wordline and a ground node and an n-channel diode-connected transistor having a source-drain path connected between a positive supply node and a gate terminal of the n-channel pull-down transistor. The n-channel diode-connected transistor is configured to apply a biasing voltage to the gate terminal of the n-channel pull-down transistor that is a relatively lower voltage for relatively lower temperatures and a relatively higher voltage for relatively higher temperatures.