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    Integrated semiconductor DRAM-type memory device and corresponding fabrication process
    11.
    发明申请
    Integrated semiconductor DRAM-type memory device and corresponding fabrication process 有权
    集成半导体DRAM型存储器件及相应的制造工艺

    公开(公告)号：US20030006431A1

    公开(公告)日：2003-01-09

    申请号：US10174490

    申请日：2002-06-18

    Applicant: STMicroelectronics S.A.

    Inventor： Thomas Skotnicki ,  Alexandre Villaret

    IPC: H01L031/072

    CPC classification number: H01L29/42336 ,  H01L29/788

    Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.

    Abstract translation: 集成存储器位置结构包括在晶体管的源极区域和漏极区域之间以及沟道区域和晶体管的控制栅极之间的隔离半导体层。 隔离半导体层包括由晶体管的控制栅极下方的势垒区隔开的两个势阱区。 写入电路偏置存储器位置结构以将电荷载流子选择性地限制在两个势阱区域中的一个中。 读取电路偏置存储器位置结构以测量晶体管的漏极电流，并从其中确定由电荷在一个潜在阱区中施加的存储的逻辑状态。

    Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor
    12.
    发明申请
    Method of fabricating a vertical insulated gate transistor with low overlap of the gate on the source and the drain, and an integrated circuit including this kind of transistor 有权
    制造在源极和漏极上的栅极的低重叠的垂直绝缘栅极晶体管的方法，以及包括这种晶体管的集成电路

    公开(公告)号：US20020177265A1

    公开(公告)日：2002-11-28

    申请号：US10114329

    申请日：2002-04-02

    Applicant: STMICROELECTRONICS S.A.

    Inventor： Thomas Skotnicki ,  Emmanuel Josse

    IPC: H01L021/8238

    CPC classification number: H01L29/66666 ,  H01L21/2807 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/49 ,  H01L29/7827

    Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.

    Abstract translation: 垂直晶体管在半导体衬底上包括在顶部具有源极和漏极区中的一个的垂直柱5，源极和漏极区中的另一个位于柱的外围的衬底中，栅极介电层 7位于柱的侧面和基板的顶表面上，以及位于栅极介电层上的半导体栅极。 栅极包括具有搁置在栅极电介质层7上的第一区域800的半导体块和面向源极和漏极区域的至少部分的第二区域90，并且通过电介质腔14S，14D与那些源极和漏极区域分离。

    Integrated semiconductor memory device
    13.
    发明申请
    Integrated semiconductor memory device 有权
    集成半导体存储器件

    公开(公告)号：US20020097608A1

    公开(公告)日：2002-07-25

    申请号：US10022185

    申请日：2001-12-12

    Applicant: STMICROELECTRONICS S.A.

    Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Michel Haond

    IPC: G11C011/34

    CPC classification number: H01L29/1054 ,  H01L29/0653 ,  H01L29/803

    Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

    Abstract translation: 诸如光电子器件和集成半导体存储器件的电子器件包括至少一个集成的存储器点结构，其包括埋在该结构的衬底中并设置在晶体管的绝缘栅极之下的量子阱半导体区域。 偏置电压源适于偏置该结构以使能量子阱或量子阱外的电荷的充电或放电。

    Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor
    14.
    发明申请
    Process for fabricating a MOS transistor having two gates, one of which is buried and corresponding transistor 有权
    用于制造具有两个栅极的MOS晶体管的工艺，其中一个栅极被埋入并且对应的晶体管

    公开(公告)号：US20010053569A1

    公开(公告)日：2001-12-20

    申请号：US09812717

    申请日：2001-03-20

    Applicant: STMicroelectronics S.A.

    Inventor： Thomas Skotnicki ,  Malgorzata Jurczak ,  Michel Haond

    IPC: H01L021/335

    CPC classification number: H01L29/66772 ,  H01L29/78648

    Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

    Abstract translation: 制造MOS晶体管的方法包括在绝缘体上硅衬底内形成第一栅极，形成横向覆盖第一栅极的半导体沟道区，以及在沟道区的每一侧上形成半导体漏极和源极区。 半导体沟道区域和漏极和源极区域可以通过在第一栅极的上表面上外延生长。 通道区域可以通过在通道区域下形成隧道并且用第一电介质至少部分地填充隧道而与第一栅极的上表面隔离。 第二栅极形成在沟道区域上并且横向于沟道区域。 第二栅极可以通过第二电介质与沟道区的上表面分离。

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