-
公开(公告)号：US20210183442A1
公开(公告)日：2021-06-17
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
-
公开(公告)号：US20210125668A1
公开(公告)日：2021-04-29
申请号：US17072887
申请日：2020-10-16
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti
IPC: G11C13/00
Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.
-
公开(公告)号：US10522220B2
公开(公告)日：2019-12-31
申请号：US16056818
申请日：2018-08-07
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfre′
Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.
-
公开(公告)号：US20190051348A1
公开(公告)日：2019-02-14
申请号：US16056818
申请日：2018-08-07
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfre'
IPC: G11C13/00
Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.
-
公开(公告)号：US10115460B2
公开(公告)日：2018-10-30
申请号：US15639540
申请日：2017-06-30
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfre′ , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
-
Patent Agency Ranking
16.发明授权公开(公告)号：US11380380B2
公开(公告)日：2022-07-05
申请号：US17088060
申请日：2020-11-03
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Maurizio Francesco Perroni , Cesare Torti , Guiseppe Scardino
Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.
-
17.发明授权公开(公告)号：US11289158B2
公开(公告)日：2022-03-29
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
-
18.发明申请公开(公告)号：US20210233582A1
公开(公告)日：2021-07-29
申请号：US17159381
申请日：2021-01-27
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.
-
公开(公告)号：US10255973B2
公开(公告)日：2019-04-09
申请号：US15797732
申请日：2017-10-30
Applicant: STMicroelectronics S.r.l.
Inventor： Davide Manfre , Cesare Torti , Fabio Enrico Carlo Disegni
Abstract: An embodiment memory device includes a memory array having a plurality of bit lines, a low-voltage connection path configured to connect, in an operational phase of the device, an access terminal to a selected local bit line of the plurality of bit lines, and a high-voltage connection path configured to connect, in the operational phase of the device, the access terminal to the selected local bit line, in parallel with the low-voltage connection path.
-
20.发明申请公开(公告)号：US20180122470A1
公开(公告)日：2018-05-03
申请号：US15598962
申请日：2017-05-18
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0097 , G11C2013/0045 , G11C2013/0078 , G11C2213/79 , G11C2213/82
Abstract: A non-volatile memory includes a number of bit lines, a number of source lines, and a number of memory cells of a non-volatile type. Each memory cell is coupled between a respective bit line and a respective source line. One or more discharge lines are coupled to a reference-voltage terminal. A number of controlled switches are coupled between a respective source line and a respective discharge line, which can be selectively driven for connecting the respective source line to the respective discharge line so as to form a conductive path between the respective source line and the reference-voltage terminal.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.017 seconds)
