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    FRACTIONAL BANDGAP REFERENCE VOLTAGE GENERATOR
    11.
    发明申请
    FRACTIONAL BANDGAP REFERENCE VOLTAGE GENERATOR 有权

    公开(公告)号：US20180017986A1

    公开(公告)日：2018-01-18

    申请号：US15207732

    申请日：2016-07-12

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhirup Lahiri

    IPC: G05F3/30 ,  G05F3/26

    CPC classification number: G05F3/30 ,  G05F3/262

    Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.

    Charge pump circuit for a phase locked loop
    12.
    发明授权
    Charge pump circuit for a phase locked loop 有权
    电荷泵电路用于锁相环

    公开(公告)号：US09438254B1

    公开(公告)日：2016-09-06

    申请号：US14718597

    申请日：2015-05-21

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhirup Lahiri

    IPC: H03L7/06 ,  H03L7/085

    CPC classification number: H03L7/0891 ,  H03L7/099

    Abstract: A phase-locked-loop includes a phase-frequency-detector (PFD) comparing phases of an input signal and feedback signal, and generating therefrom control signals. An attenuation circuit in series with the PFD includes a filter between a voltage-controlled-oscillator (VCO) control node and ground. A buffer is coupled to the VCO control node. An impedance network is coupled to the VCO control node and has an impedance element coupled to a first current source so voltage at the VCO control node increases when control signals indicate the phase of the input signal leads the feedback signal, and coupled to a second current source so voltage at the VCO control node decreases when control signals indicate a lagging phase. A VCO is coupled to the VCO control node to generate an output signal, with the phase of the output signal matching the input signal. The feedback signal is based upon the output signal.

    Abstract translation: 锁相环包括比较输入信号和反馈信号的相位的相位频率检测器（PFD），并从其产生控制信号。 与PFD串联的衰减电路包括压控振荡器（VCO）控制节点和地之间的滤波器。 缓冲器耦合到VCO控制节点。 阻抗网络耦合到VCO控制节点并且具有耦合到第一电流源的阻抗元件，因此当控制信号指示输入信号的相位引导反馈信号并耦合到第二电流时，VCO控制节点处的电压增加 当控制信号指示滞后相位时，VCO控制节点处的源极电压降低。 VCO耦合到VCO控制节点以产生输出信号，输出信号的相位与输入信号匹配。 反馈信号基于输出信号。

    Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature
    13.
    发明授权
    Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature 有权
    锁相环（PLL）电路，具有过程，电压和温度的补偿带宽

    公开(公告)号：US09325324B1

    公开(公告)日：2016-04-26

    申请号：US14573002

    申请日：2014-12-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Nitin Gupta ,  Anand Kumar ,  Abhirup Lahiri

    IPC: H03L7/00 ,  H03L1/02 ,  H03L7/093 ,  H03L7/18 ,  H03L7/099 ,  H03L7/107

    CPC classification number: H03L7/099 ,  H03L1/00 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/113 ,  H03L7/18

    Abstract: A phase locked loop (PLL) circuit includes a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control signal responsive to the phase comparison and an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback signal is derived from said output signal. The PLL circuit further operates in a calibration mode of operation wherein the oscillator circuit operates in a frequency locked loop mode to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit across process, voltage and temperature in response to the frequency comparison. Furthermore, bias current for a charge pump within the phase comparison circuit is calibrated during calibration mode of operation to match a temperature independent reference current.

    Abstract translation: 锁相环（PLL）电路包括相位比较电路，其被配置为将输入信号的相位与反馈信号的相位进行比较，并响应于相位比较产生控制信号，以及振荡器电路，被配置为产生频率的输出信号 由所述控制信号设置，其中所述反馈信号从所述输出信号导出。 PLL电路进一步在校准操作模式下工作，其中振荡器电路以频率锁定环路模式操作，以将输入信号的频率与输出信号的频率进行比较，并将振荡器电路的增益集中在过程，电压和温度之间 响应频率比较。 此外，相位比较电路内的电荷泵的偏置电流在校准操作模式下进行校准，以匹配与温度无关的参考电流。

    Current reused stacked ring oscillator and injection locked divider, injection locked multiplier
    14.
    发明授权
    Current reused stacked ring oscillator and injection locked divider, injection locked multiplier 有权
    电流重复堆叠环形振荡器和注入锁定分频器，注入锁定倍频器

    公开(公告)号：US09018987B1

    公开(公告)日：2015-04-28

    申请号：US14090744

    申请日：2013-11-26

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhirup Lahiri

    IPC: H03B19/00 ,  H03L7/00 ,  H03K3/03 ,  H03K23/54 ,  H03L7/099

    CPC classification number: H03L7/0995 ,  H03K3/0315 ,  H03K23/54 ,  H03L7/24

    Abstract: A phase locked loop includes a voltage controlled oscillator and a frequency divider or frequency multiplier. The voltage controlled oscillator and the frequency divider/multiplier are coupled together in a stacked configuration. A drive current is supplied to the voltage controlled oscillator. The drive current passes from the voltage controlled oscillator to the frequency divider/multiplier, thereby driving the frequency divider/multiplier with the same drive current that was supplied to the voltage controlled oscillator.

    Abstract translation: 锁相环包括压控振荡器和分频器或倍频器。 压控振荡器和分频器/乘法器以堆叠配置耦合在一起。 驱动电流被提供给压控振荡器。 驱动电流从压控振荡器传递到分频器/乘法器，从而以提供给压控振荡器的相同驱动电流来驱动分频器/乘法器。

    Fractional bandgap reference voltage generator
    15.
    发明授权
    Fractional bandgap reference voltage generator 有权

    公开(公告)号：US10222819B2

    公开(公告)日：2019-03-05

    申请号：US15866651

    申请日：2018-01-10

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhirup Lahiri

    IPC: G05F3/30 ,  G05F3/26

    Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.

    Charge pump circuit for a phase locked loop
    18.
    发明授权
    Charge pump circuit for a phase locked loop 有权
    电荷泵电路用于锁相环

    公开(公告)号：US09559708B2

    公开(公告)日：2017-01-31

    申请号：US15229322

    申请日：2016-08-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhirup Lahiri

    IPC: H03L7/06 ,  H03L7/089 ,  H03L7/099

    CPC classification number: H03L7/0891 ,  H03L7/099

    Abstract: Disclosed herein is a circuit including a phase frequency detector (PFD) configured to compare phases of an input signal and a feedback signal, and to generate first and second control signals as a function of that comparison. An attenuation circuit includes a capacitor coupled in series between a node and a switching node, and is configured to charge the capacitor and disconnect the switching node from ground based on assertion of the first control signal, and discharge the capacitor and connect the switching node to ground based on assertion of the second control signal.

    Abstract translation: 这里公开了一种电路，其包括被配置为比较输入信号和反馈信号的相位的相位频率检测器（PFD），并且作为该比较的函数产生第一和第二控制信号。 衰减电路包括串联耦合在节点和开关节点之间的电容器，并且被配置为基于第一控制信号的断言对电容器充电并将开关节点与地断开，并且将开关节点放电到 基于第二控制信号的断言接地。

    CHARGE PUMP CIRCUIT FOR A PHASE LOCKED LOOP
    19.
    发明申请
    CHARGE PUMP CIRCUIT FOR A PHASE LOCKED LOOP 审中-公开
    充电泵电路用于相位锁定环路

    公开(公告)号：US20160344395A1

    公开(公告)日：2016-11-24

    申请号：US15229322

    申请日：2016-08-05

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhirup Lahiri

    IPC: H03L7/089 ,  H03L7/099

    CPC classification number: H03L7/0891 ,  H03L7/099

    Abstract: Disclosed herein is a circuit including a phase frequency detector (PFD) configured to compare phases of an input signal and a feedback signal, and to generate first and second control signals as a function of that comparison. An attenuation circuit includes a capacitor coupled in series between a node and a switching node, and is configured to charge the capacitor and disconnect the switching node from ground based on assertion of the first control signal, and discharge the capacitor and connect the switching node to ground based on assertion of the second control signal.

    Abstract translation: 这里公开了一种电路，其包括被配置为比较输入信号和反馈信号的相位的相位频率检测器（PFD），并且作为该比较的函数产生第一和第二控制信号。 衰减电路包括串联耦合在节点和开关节点之间的电容器，并且被配置为对电容器充电并且基于第一控制信号的断言将开关节点与地断开，并且将开关节点放电到 基于第二控制信号的断言接地。

    Capacitance multiplier and loop filter noise reduction in a PLL
    20.
    发明授权
    Capacitance multiplier and loop filter noise reduction in a PLL 有权
    PLL中的电容乘法器和环路滤波器降噪

    公开(公告)号：US09294106B2

    公开(公告)日：2016-03-22

    申请号：US14323794

    申请日：2014-07-03

    Applicant: STMicroelectronics International N.V.

    Inventor： Abhirup Lahiri ,  Nitin Gupta

    IPC: H03L7/06 ,  H03L7/089 ,  H03L7/093

    CPC classification number: H03L7/093 ,  H03L7/089

    Abstract: According to an embodiment, a circuit includes a first charge pump configured to generate a first current at a first node, a second charge pump configured to generate a second current at a second node, a loop filter coupled between the first and second nodes, the loop filter including a first filter path coupled to the first node, a second filter path coupled to the second node, and an isolation buffer interposed between the first and second filter paths. The second current at the second node is different than the first current at the first node. The circuit further includes an oscillator configured to apply a first gain to an output of the first filter path and a second gain to an output of the second filter path.

    Abstract translation: 根据实施例，电路包括被配置为在第一节点处产生第一电流的第一电荷泵，被配置为在第二节点处产生第二电流的第二电荷泵，耦合在第一和第二节点之间的环路滤波器， 环路滤波器，包括耦合到第一节点的第一滤波器路径，耦合到第二节点的第二滤波器路径以及插在第一和第二滤波器路径之间的隔离缓冲器。 第二节点处的第二个电流与第一节点处的第一个电流不同。 该电路还包括一个振荡器，被配置为对第一滤波器路径的输出施加第一增益，并将第二增益应用于第二滤波器路径的输出。

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