公开(公告)号：US09312285B2

公开(公告)日：2016-04-12

申请号：US14480751

申请日：2014-09-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Young-Wook Lee ,  Jang-Soo Kim

IPC: G02F1/1343 ,  H01L27/12 ,  G02F1/1365 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1365 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136222 ,  G02F2001/13629 ,  H01L27/1248

Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film. transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

Abstract translation: 薄膜晶体管阵列面板包括基板; 形成在所述基板上的多条栅极线; 与栅极线相交的多条数据线; 连接到栅极线和数据线的多个薄膜晶体管; 形成在栅极线，数据线和薄膜的上部的多个滤色器。 晶体管 形成在滤色器上并且包括透明导体的公共电极; 钝化层，其形成在所述公共电极的上部; 以及形成在钝化层的上部并且连接到每个薄膜晶体管的漏电极的多个像素电极。

公开(公告)号：US08836878B2

公开(公告)日：2014-09-16

申请号：US13951543

申请日：2013-07-26

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Jang-Soo Kim

IPC: G02F1/136 ,  G02F1/1362 ,  H01L27/12

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1365 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136222 ,  G02F2001/13629 ,  H01L27/1248

Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

Abstract translation: 薄膜晶体管阵列面板包括基板; 形成在所述基板上的多条栅极线; 与栅极线相交的多条数据线; 连接到栅极线和数据线的多个薄膜晶体管; 形成在栅极线，数据线和薄膜晶体管的上部的多个滤色器; 形成在滤色器上并且包括透明导体的公共电极; 钝化层，其形成在所述公共电极的上部; 以及形成在钝化层的上部并且连接到每个薄膜晶体管的漏电极的多个像素电极。

公开(公告)号：US11804495B2

公开(公告)日：2023-10-31

申请号：US17886489

申请日：2022-08-12

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/127 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/1288 ,  H01L29/78693 ,  H01L29/7869

Abstract: A substrate including a first signal line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a second signal line intersecting the first signal line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer pattern and spaced apart from the second electrode, and an insulator comprising a first portion disposed between the first signal line and the second signal line, and at least partially overlapping with both of the first signal line and the second signal line.

公开(公告)号：US11437412B2

公开(公告)日：2022-09-06

申请号：US17124497

申请日：2020-12-17

Applicant: Samsung Display Co., Ltd.

Inventor： Young-Wook Lee ,  Woo-Geun Lee ,  Ki-Won Kim ,  Hyun-Jung Lee ,  Ji-Soo Oh

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768

Abstract: A substrate including a gate line and a first electrode disposed on the substrate, an oxide semiconductor layer pattern overlapping the first electrode, an insulating layer disposed between the first electrode and the oxide semiconductor layer pattern, a data line intersecting the gate line, a second electrode electrically connected to the oxide semiconductor layer pattern, a third electrode electrically connected to the oxide semiconductor layer, the third electrode spaced apart from the second electrode, and an insulating pattern including a first portion which is disposed between the gate line and the data line and at least partially overlaps with both of the gate line and the data line.

公开(公告)号：US09823531B2

公开(公告)日：2017-11-21

申请号：US14277526

申请日：2014-05-14

Applicant: Samsung Display Co., Ltd.

Inventor： Tae-Young Choi ,  Bo Sung Kim ,  Jae Woo Park ,  Hee Jun Byeon ,  Young-Wook Lee ,  Moon-Keun Choi

IPC: G02F1/1362 ,  H01L27/12 ,  H01L27/02

CPC classification number: G02F1/136286 ,  G02F1/136204 ,  H01L27/0288 ,  H01L27/124

Abstract: A thin film transistor array panel includes: gate lines; data lines insulated from and crossing the gate lines; and shorting bars disposed outside of a display area in which the gate lines cross the data lines. The shorting bars overlap portions of the data lines disposed outside of the display area. The shorting bar includes a semiconductor material.

公开(公告)号：US09589993B2

公开(公告)日：2017-03-07

申请号：US14984448

申请日：2015-12-30

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeon Jun Lee ,  Katsumi Abe ,  Young-Wook Lee

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/24 ,  H01L23/528 ,  H01L23/31 ,  H01L29/66 ,  H01L29/786 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L27/124 ,  G09G3/3677 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2320/0214 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/3171 ,  H01L23/528 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: A thin film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a voltage wire disposed on the substrate, a gate insulating layer disposed on the first gate electrode and the voltage wire, a semiconductor pattern including an oxide semiconductor material disposed on the gate insulating layer, a source electrode and a drain electrode disposed at a distance from each other on the semiconductor pattern, a first passivation layer disposed on the source electrode and the drain electrode, and a first electrode disposed on the first passivation layer and connected with the voltage wire.

Abstract translation: 薄膜晶体管阵列面板包括衬底，设置在衬底上的第一栅极电极，设置在衬底上的电压线，设置在第一栅电极和电压线上的栅极绝缘层，包括氧化物半导体材料的半导体图案 设置在所述栅极绝缘层上，在所述半导体图案上彼此间隔设置的源电极和漏电极，设置在所述源电极和所述漏电极上的第一钝化层，以及设置在所述第一钝化层上的第一电极 并与电压线连接。

公开(公告)号：US20150318312A1

公开(公告)日：2015-11-05

申请号：US14799060

申请日：2015-07-14

Applicant: Samsung Display Co.,Ltd

Inventor： Pil-Sang Yun ,  Ki-Won Kim ,  Hye-Young Ryu ,  Woo-Geun Lee ,  Seung-Ha Choi ,  Jae-Hyoung Youn ,  Kyoung-Jae Chung ,  Young-Wook Lee ,  Je-Hun Lee ,  Kap-Soo Yoon ,  Do-Hyun Kim ,  Dong-Ju Yang ,  Young-Joo Choi

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/44 ,  H01L21/441 ,  H01L21/465 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor panel includes an insulating substrate, a gate insulating layer disposed on the insulating substrate, an oxide semiconductor layer disposed on the gate insulating layer, an etch stopper disposed on the oxide semiconductor layer, and a source electrode and a drain electrode disposed on the etch stopper.

公开(公告)号：US08835216B2

公开(公告)日：2014-09-16

申请号：US13932425

申请日：2013-07-01

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang Yun ,  Young-Wook Lee ,  Woo-Geun Lee

IPC: H01L21/34 ,  H01L27/12 ,  H01L21/467 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L21/467 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/7869

Abstract: An oxide thin-film transistor (TFT) substrate that includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.

Abstract translation: 一种氧化物薄膜晶体管（TFT）基板，包括：基板，栅极线，数据线，氧化物TFT和像素电极。 氧化物TFT的氧化物层包括具有半导体特性的第一区域和沟道，以及导电并围绕第一区域的第二区域。 第一区域的一部分电连接到像素电极，并且第二区域电连接到数据线。

公开(公告)号：US20130295718A1

公开(公告)日：2013-11-07

申请号：US13932425

申请日：2013-07-01

Applicant: Samsung Display Co., Ltd.

Inventor： Pil-Sang YUN ,  Young-Wook Lee ,  Woo-Geun Lee

IPC: H01L21/467

CPC classification number: H01L21/467 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/7869

Abstract: An oxide thin-film transistor (TFT) substrate that includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.

Abstract translation: 一种氧化物薄膜晶体管（TFT）基板，包括：基板，栅极线，数据线，氧化物TFT和像素电极。 氧化物TFT的氧化物层包括具有半导体特性的第一区域和沟道，以及导电并围绕第一区域的第二区域。 第一区域的一部分电连接到像素电极，并且第二区域电连接到数据线。

公开(公告)号：US08563368B2

公开(公告)日：2013-10-22

申请号：US13758716

申请日：2013-02-04

Applicant: Samsung Display Co., Ltd

Inventor： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC: H01L21/00

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.