公开(公告)号：US20240203793A1

公开(公告)日：2024-06-20

申请号：US18141313

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Sun Kim ,  Wonhyuk Hong ,  Jongjin Lee ,  Buhyun Ham ,  Kang-ill Seo

IPC: H01L21/768 ,  H01L21/74

CPC classification number: H01L21/76897 ,  H01L21/74 ,  H01L21/76834 ,  H01L21/76885

Abstract: In order to achieve higher contact quality for backside power distribution networks, provided is a backside contact to a semiconductor device having a positive slope and a dielectric sidewall liner, and methods for making the same.

公开(公告)号：US11270944B2

公开(公告)日：2022-03-08

申请号：US16940933

申请日：2020-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Rakhwan Kim ,  Eun-Ji Jung

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US12199038B2

公开(公告)日：2025-01-14

申请号：US18343784

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US12087669B1

公开(公告)日：2024-09-10

申请号：US18543111

申请日：2023-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehong Lee ,  Sooyoung Park ,  Wonhyuk Hong ,  Kang-Ill Seo

IPC: H01L21/00 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/07 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0727 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices and methods of forming the same. As an example, an integrated circuit device may include a substrate; a first transistor structure on the substrate; a second transistor structure stacked in a vertical direction on the first transistor structure; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; and a diode structure on the substrate and adjacent to the first transistor structure in a horizontal direction. The diode structure may be part of a discharging path between a gate electrode of the second transistor structure and the substrate. The discharging path may extend through the isolation layer.

公开(公告)号：US20240290689A1

公开(公告)日：2024-08-29

申请号：US18215985

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan YUN ,  Wonhyuk Hong ,  Keumseok Park ,  Se Jung Park ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Provided is a semiconductor device including: a channel structure; source/drain regions connected by the channel structure; and a backside contact structure formed below at least one of the source/drain region, wherein, in a 1st-direction cross section view, a width of an upper portion of the backside contact structure close to the source/drain region is smaller than a width of a lower portion of the backside contact structure distant from the source/drain region, wherein, in a 2nd-direction cross-section view, widths of the upper portion and the lower portion of the backside contact structure are substantially uniform along a vertical downward direction, and wherein the 1st direction intersects the 2nd direction.

公开(公告)号：US20240096984A1

公开(公告)日：2024-03-21

申请号：US18160341

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Tae Sun Kim ,  Wonhyuk Hong ,  Seungchan Yun ,  Kang-Ill Seo

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/775

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.

公开(公告)号：US20240079330A1

公开(公告)日：2024-03-07

申请号：US18169905

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Jaejik Baek ,  Myunghoon Jung ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L23/5286 ,  H01L21/84 ,  H01L27/12 ,  H01L21/823475

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower insulating structure, a transistor on the lower insulating structure, the transistor including a source/drain region, a power rail structure in the lower insulating structure, and a power contact structure that is on the power rail structure and electrically connects the source/drain region to the power rail structure. The power contact structure may include a lower portion that is in the power rail structure.

公开(公告)号：US20230326858A1

公开(公告)日：2023-10-12

申请号：US17887203

申请日：2022-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Buhyun HAM ,  Byounghak Hong ,  Myunghoon Jung ,  Wonhyuk Hong ,  Seungyoung Lee ,  Kang-ill Seo

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L23/5286 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/5329 ,  H01L21/76897

Abstract: Provided is a semiconductor chip architecture including a wafer, a front-end-of-line (FEOL) layer on a first side of the wafer, the FEOL layer including a semiconductor device and an interlayer dielectric (ILD) structure on the semiconductor device on the first side of the wafer, a shallow trench isolation (STI) structure in the wafer, and the wafer, a middle-of-line (MOL) layer provided on the first FEOL layer, the MOL layer including a contact and a via connected to the contact, an insulating layer on the first side of the wafer and adjacent to the via in a horizontal direction, a power rail penetrating the wafer from a second side of the wafer opposite to the first side, wherein the via extends through the ILD structure, the STI structure, and the wafer in a vertical direction to contact the power rail.

公开(公告)号：US11728268B2

公开(公告)日：2023-08-15

申请号：US17458873

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.