公开(公告)号：US20240429130A1

公开(公告)日：2024-12-26

申请号：US18375186

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Sun Kim ,  Wonhyuk Hong ,  Jongjin Lee ,  Kang-ill Seo ,  Jason Martineau

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a 1st source/drain region; a 2nd source/drain region; a channel structure connecting the 1st source/drain region to the 2nd source/drain region; a gate structure surrounding the channel structure; a backside contact structure, below the 1st source/drain region, connected to the 1st source/drain region; and a 1st backside spacer at a lateral side of the backside contact structure.

公开(公告)号：US20230352405A1

公开(公告)日：2023-11-02

申请号：US17820949

申请日：2022-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Janggeun Lee ,  Jaemyung Choi ,  Wonhyuk Hong ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L21/76819 ,  H01L23/53295 ,  H01L23/53228 ,  H01L23/53257

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a first insulating layer and a metal via that is in the first insulating layer. The integrated circuit device includes a second insulating layer on the first insulating layer. The integrated circuit device includes a conductive material that is between sidewalls of the second insulating layer and on the metal via. Moreover, the integrated circuit device includes a metal line that is on the conductive material and/or the second insulating layer. Related methods of forming integrated circuit devices are also provided.

公开(公告)号：US20230369111A1

公开(公告)日：2023-11-16

申请号：US17929833

申请日：2022-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEMYUNG CHOI ,  Janggeun Lee ,  Wonhyuk Hong ,  Kang-Ill Seo

IPC: H01L21/768 ,  H01L21/3065 ,  H01L23/532

CPC classification number: H01L21/76861 ,  H01L21/3065 ,  H01L23/53261 ,  H01L23/53247

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing an underlying structure including a first insulating layer and forming a first metal structure, a first adhesion pattern, and a second insulating layer thereon. The second insulating layer may be on a side surface of the first metal structure, the first metal structure may include a metal pattern and a second adhesion pattern between the first insulating layer and the metal pattern, and the first adhesion pattern contacts side surfaces of the metal pattern and the second adhesion pattern. The methods may also include forming a second metal structure on the first metal structure. The metal pattern may include a contact portion protruding upwardly beyond an upper surface of the second insulating layer or may include an upper surface recessed with respect to the upper surface of the second insulating layer.

公开(公告)号：US20230343707A1

公开(公告)日：2023-10-26

申请号：US18343784

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US12199042B2

公开(公告)日：2025-01-14

申请号：US17590238

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Rakhwan Kim ,  Eun-Ji Jung

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20240413213A1

公开(公告)日：2024-12-12

申请号：US18378943

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keumseok PARK ,  Wonhyuk Hong ,  Kang-ill Seo

IPC: H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a 1st source/drain region connected to a 1st channel structure; a 2nd source/drain region, above the 1st source/drain region, connected to a 2nd channel structure above the 1st channel structure; a backside contact structure on a bottom surface of the 1st source/drain region; and a backside isolation structure surrounding the backside contact structure, wherein the bottom surface of the 1st source/drain region is at a level below a top surface of the backside isolation structure.

公开(公告)号：US20220238439A1

公开(公告)日：2022-07-28

申请号：US17458873

申请日：2021-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Eui Bok Lee ,  Rakhwan Kim ,  Woojin Jang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a transistor on a substrate, a first metal layer that is on the transistor and includes a lower wire electrically connected to the transistor, and a second metal layer on the first metal layer. The second metal layer includes an upper wire that is electrically connected to the lower wire and includes a via structure in a via hole and a line structure in a line trench. The via structure includes a via portion that is in the via hole and is coupled to the lower wire, and a barrier portion that vertically extends from the via portion to cover an inner surface of the line trench. The barrier portion is between the line structure and an insulating layer of the second metal layer. The barrier portion is thicker at its lower level than at its upper level.

公开(公告)号：US12255248B2

公开(公告)日：2025-03-18

申请号：US18540280

申请日：2023-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Taesun Kim ,  Myunghoon Jung ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A system and a method are disclosed for forming a bottle-neck shaped backside contact structure in a semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side partially within the first source/drain structure, a second side contacting a backside power rail, and a liner extending from the first side to the backside power rail. The liner includes a first region comprised of either a Ta silicide liner or a Ti silicide liner, a second region comprised of a Ti/TiN liner and a third region comprised of either a Ta silicide liner or a Ti silicide liner. The backside contact structure includes a first portion having a positive slope and a second portion, adjacent to the first portion, having no slope.

公开(公告)号：US20240421154A1

公开(公告)日：2024-12-19

申请号：US18488412

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Wonhyuk Hong ,  Tae Sun Kim ,  Panjae Park ,  Kang-ill Seo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including first and second source/drain regions spaced apart from each other in a horizontal direction, a backside power distribution network structure (BSPDNS), a substrate between the first and second source/drain regions and the BSPDNS, a backside contact that is in the substrate and is overlapped by the first source/drain region, a placeholder that is in the substrate and is overlapped by the second source/drain region, and a cavity in the substrate between the backside contact and the placeholder.

公开(公告)号：US20240282670A1

公开(公告)日：2024-08-22

申请号：US18221696

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Yang ,  Wonhyuk Hong ,  Myunghoon Jung ,  Jongjin Lee ,  Jaejik Baek ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes: at least one transistor comprising source/drain regions and 1st gate structure; a contact isolation layer below the 1st gate structure; and a backside contact plug connected to at least one of the 1st source/drain regions, wherein the backside contact plug is formed below the 1st source/drain region and extended to a region below the 1st gate structure, and isolated from the 1st gate structure by the contact isolation layer.