公开(公告)号：US12199042B2

公开(公告)日：2025-01-14

申请号：US17590238

申请日：2022-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Rakhwan Kim ,  Eun-Ji Jung

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

公开(公告)号：US20240429130A1

公开(公告)日：2024-12-26

申请号：US18375186

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Sun Kim ,  Wonhyuk Hong ,  Jongjin Lee ,  Kang-ill Seo ,  Jason Martineau

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a 1st source/drain region; a 2nd source/drain region; a channel structure connecting the 1st source/drain region to the 2nd source/drain region; a gate structure surrounding the channel structure; a backside contact structure, below the 1st source/drain region, connected to the 1st source/drain region; and a 1st backside spacer at a lateral side of the backside contact structure.

公开(公告)号：US20240319761A1

公开(公告)日：2024-09-26

申请号：US18609073

申请日：2024-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeyoung Lee ,  Byungsu Kim ,  Youngsan Kim ,  Jaegon Lee ,  Jaehoon Kim ,  Byeongho Lee ,  Jongjin Lee ,  Wookyeong Jeong

IPC: G06F1/08 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H03K5/133 ,  H03K5/1534

CPC classification number: G06F1/08 ,  H03K5/133 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225 ,  H03K5/1534

Abstract: A semiconductor device includes an intellectual property (IP) block configured to operate based on a first clock signal and a power voltage, a clock gating circuit configured to operate based on the power voltage, and generate the first clock signal by selectively performing clock gating on a second clock signal based on an enable signal, and a critical path monitor (CPM) configured to generate a digital code having a value, which varies according to a voltage drop of the power voltage, and activate the enable signal based on a comparison of the value of the digital code with a reference value.

公开(公告)号：US11967554B2

公开(公告)日：2024-04-23

申请号：US18053487

申请日：2022-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Kyungwook Kim ,  Rakhwan Kim ,  Seungyong Yoo ,  Eun-Ji Jung

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/45

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/45

Abstract: Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.

公开(公告)号：US12034373B2

公开(公告)日：2024-07-09

申请号：US17575249

申请日：2022-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwook Park ,  Joonseok Park ,  Jongjin Lee ,  Horang Jang

IPC: H02M3/158 ,  G06F13/42 ,  H02M3/157

CPC classification number: H02M3/1584 ,  G06F13/4282 ,  H02M3/157 ,  G06F2213/0016 ,  G06F2213/0038

Abstract: An electronic device includes a system on chip (SoC) and a power management integrated circuit (PMIC). The SoC includes a plurality of power domains and a dynamic voltage and frequency scaling (DVFS) controller which performs DVFS on the power domains The PMIC includes direct current (DC)-DC converters and a control logic which controls the plurality of DC-DC converters, and each of the DC-DC converters provides a corresponding output voltage to a respective one of the power domains. The control logic designates a target DC-DC converter which provides a target output voltage having a target level as a global DC-DC converter and provides the target output voltage to a power domain corresponding the global DC-DC converter and to at least one first power domain consuming the target output voltage, from among the plurality of power domains, by sharing the target output voltage provided by the global DC-DC converter.

公开(公告)号：US20240096984A1

公开(公告)日：2024-03-21

申请号：US18160341

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Tae Sun Kim ,  Wonhyuk Hong ,  Seungchan Yun ,  Kang-Ill Seo

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/775

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.

公开(公告)号：US20240079330A1

公开(公告)日：2024-03-07

申请号：US18169905

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Jaejik Baek ,  Myunghoon Jung ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L23/5286 ,  H01L21/84 ,  H01L27/12 ,  H01L21/823475

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a lower insulating structure, a transistor on the lower insulating structure, the transistor including a source/drain region, a power rail structure in the lower insulating structure, and a power contact structure that is on the power rail structure and electrically connects the source/drain region to the power rail structure. The power contact structure may include a lower portion that is in the power rail structure.

公开(公告)号：US09690200B2

公开(公告)日：2017-06-27

申请号：US14867292

申请日：2015-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjoon Hong ,  Jongjin Lee ,  Hikuk Lee ,  Sangdon Jang ,  Inbae Chang

IPC: G03B27/54 ,  G03F7/16 ,  G03F7/20

CPC classification number: G03F7/16 ,  G03F7/70383 ,  G03F7/70791 ,  G03F7/7085

Abstract: An optical apparatus and a manufacturing method using the optical apparatus are disclosed. The optical apparatus includes a stage supporting a substrate, first optical systems providing a first light onto the substrate, a gantry supporting the first optical systems to transfer them on the stage, and second optical systems disposed between the gantry and the stage and detecting displacement of the first optical systems. Each of the second optical systems includes a beam source generating a second light different with the first light, and sensor arrays for sensing the second light provided to the first optical systems to detect displacement of the first optical systems.

公开(公告)号：US12255248B2

公开(公告)日：2025-03-18

申请号：US18540280

申请日：2023-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyuk Hong ,  Jongjin Lee ,  Taesun Kim ,  Myunghoon Jung ,  Kang-ill Seo

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A system and a method are disclosed for forming a bottle-neck shaped backside contact structure in a semiconductor device, wherein the bottle-neck shaped backside contact structure has a first side partially within the first source/drain structure, a second side contacting a backside power rail, and a liner extending from the first side to the backside power rail. The liner includes a first region comprised of either a Ta silicide liner or a Ti silicide liner, a second region comprised of a Ti/TiN liner and a third region comprised of either a Ta silicide liner or a Ti silicide liner. The backside contact structure includes a first portion having a positive slope and a second portion, adjacent to the first portion, having no slope.

公开(公告)号：US20240421154A1

公开(公告)日：2024-12-19

申请号：US18488412

申请日：2023-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Wonhyuk Hong ,  Tae Sun Kim ,  Panjae Park ,  Kang-ill Seo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including first and second source/drain regions spaced apart from each other in a horizontal direction, a backside power distribution network structure (BSPDNS), a substrate between the first and second source/drain regions and the BSPDNS, a backside contact that is in the substrate and is overlapped by the first source/drain region, a placeholder that is in the substrate and is overlapped by the second source/drain region, and a cavity in the substrate between the backside contact and the placeholder.