公开(公告)号：US20230361112A1

公开(公告)日：2023-11-09

申请号：US17936127

申请日：2022-09-28

Applicant: Samsung Electronics Co.; Ltd.

Inventor： BYOUNGHAK HONG ,  Gunho Jo ,  Sooyoung Park ,  Hyoeun Park ,  WookHyun Kwon ,  Jaehong Lee ,  Kang-Ill Seo

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/735 ,  H01L29/861

CPC classification number: H01L27/067 ,  H01L29/0673 ,  H01L29/735 ,  H01L29/8613

Abstract: Integrated circuit devices including a bipolar junction transistor (BJT) and/or a P-N junction diode are provided. The integrated circuit devices may include a first stack including first and second semiconductor regions that are spaced apart from each other in a horizontal direction and have a first conductivity type and a plurality of nano-semiconductor layers that are stacked in a vertical direction and are between the first and second semiconductor regions. The plurality of nano-semiconductor layers each have a second conductivity type, and the first semiconductor region may include a side surface facing the plurality of nano-semiconductor layers. The integrated circuit device may also include a vertical semiconductor layer having the second conductivity type and a conductive contact that contacts the plurality of nano-semiconductor layers. The vertical semiconductor layer may contact the side surface of the first semiconductor region and the plurality of nano-semiconductor layers.

公开(公告)号：US11322602B2

公开(公告)日：2022-05-03

申请号：US16794358

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi Chan Jun ,  Kang-Ill Seo ,  Jeong Hyuk Yim

IPC: H01L29/66 ,  H01L29/78

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.

公开(公告)号：US09614068B2

公开(公告)日：2017-04-04

申请号：US14843231

申请日：2015-09-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Ill Seo

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: A semiconductor device includes a first active region, a field insulating layer disposed in the first active region, a first nanowire pattern disposed on the first active region and extended in a first direction, and a first gate disposed on the first active region and extended in a second direction crossing the first direction. The first gate covers the first nanowire pattern. The semiconductor device further includes a source or drain epitaxial layer disposed on at least one side of the first nanowire pattern. The first gate includes a first region disposed on the first nanowire pattern and having a first width, and a second region disposed beneath the first nanowire pattern and having a second width wider than the first width.

公开(公告)号：US09570434B2

公开(公告)日：2017-02-14

申请号：US15217531

申请日：2016-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Jae Kang ,  Jin-Wook Lee ,  Kang-Ill Seo ,  Yong-Min Cho

IPC: H01L27/088 ,  H01L27/02 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  G03F7/70 ,  H01L21/0274 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/0207

Abstract: Provided are a semiconductor device and a fabricating method thereof. The fabricating method includes forming first to fourth fins, each extending in a first direction, to be spaced apart in a second direction intersecting the first direction, forming first and second gate lines, each extending in the second direction, on the first to fourth fins to be spaced apart in the first direction, forming a first contact on the first gate line between the first and second fins, forming a second contact on the first gate line between the third and fourth fins, forming a third contact on the second gate line between the first and second fins, forming a fourth contact on the second gate line between the third and fourth fins and forming a fifth contact on the first to fourth contacts so as to overlap with the second contact and the third contact and so as not to overlap with the first contact and the fourth contact, wherein the fifth contact is arranged to diagonally traverse a quadrangle defined by the first to fourth contacts.

Abstract translation: 提供一种半导体器件及其制造方法。 制造方法包括：形成第一至第四鳍片，每个翼片沿第一方向延伸，沿与第一方向相交的第二方向间隔开，形成第一和第二栅极线，每个沿第二方向延伸，第一至第四鳍片 在第一方向上间隔开，在第一和第二鳍之间的第一栅极线上形成第一接触，在第三和第四鳍之间的第一栅极线上形成第二接触，在第二栅极线上形成第三接触 在第一和第二散热片之间，在第三和第四鳍之间的第二栅极线上形成第四触点，并在第一至第四触点上形成第五触点，以便与第二触点和第三触点重叠， 与第一触点和第四触点重叠，其中第五触点布置成对角地横过由第一至第四触点限定的四边形。

公开(公告)号：US20160380084A1

公开(公告)日：2016-12-29

申请号：US15234484

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-HYUK KIM ,  Kang-Ill Seo ,  Hyun-Jae Kang ,  Deok-Han Bae

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

公开(公告)号：US12200920B2

公开(公告)日：2025-01-14

申请号：US17816809

申请日：2022-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inchan Hwang ,  Jaemyung Choi ,  Kang-Ill Seo

IPC: G11C16/04 ,  G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a static random access memory (SRAM) unit. The SRAM unit may include a first inverter on a substrate and a power distribution network (PDN) structure including a first power rail and a second power rail. The substrate may extend between the first inverter and the PDN structure. The first inverter may include a first upper transistor including a first upper source/drain region, a first lower transistor between the substrate and the first upper transistor and including a first lower source/drain region, a first power contact extending through the substrate and electrically connecting the first upper source/drain region to the first power rail, and a second power contact extending through the substrate and electrically connecting the first lower source/drain region to the second power rail.

公开(公告)号：US12119351B2

公开(公告)日：2024-10-15

申请号：US17508704

申请日：2021-10-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Il Bae ,  Kang-Ill Seo

IPC: H01L27/092 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/31053 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure on a substrate. A sacrificial layer pattern is formed on the fin structure. An active layer pattern is formed on the sacrificial layer pattern. A dummy gate pattern is formed on the active layer pattern. A spacer is formed on the dummy gate pattern. A source/drain structure is formed on the active layer pattern using an epitaxial growth process. An interlayer dielectric layer is formed on the dummy gate pattern and the active layer pattern. The interlayer dielectric layer is planarized to expose the dummy gate pattern. The dummy gate pattern is removed to expose the active layer pattern and the sacrificial layer pattern. The exposed sacrificial layer pattern is removed to form a through-hole between the exposed active layer pattern and the fin structure, the second portion of the sacrificial layer pattern is not removed.

公开(公告)号：US11901363B2

公开(公告)日：2024-02-13

申请号：US17382149

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Myunggil Kang ,  Kang-Ill Seo

IPC: H01L27/12 ,  H01L23/535 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/06 ,  H01L27/092 ,  G01R27/02

CPC classification number: H01L27/1203 ,  G01R27/02 ,  H01L23/535 ,  H01L27/1211

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US20230369111A1

公开(公告)日：2023-11-16

申请号：US17929833

申请日：2022-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEMYUNG CHOI ,  Janggeun Lee ,  Wonhyuk Hong ,  Kang-Ill Seo

IPC: H01L21/768 ,  H01L21/3065 ,  H01L23/532

CPC classification number: H01L21/76861 ,  H01L21/3065 ,  H01L23/53261 ,  H01L23/53247

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing an underlying structure including a first insulating layer and forming a first metal structure, a first adhesion pattern, and a second insulating layer thereon. The second insulating layer may be on a side surface of the first metal structure, the first metal structure may include a metal pattern and a second adhesion pattern between the first insulating layer and the metal pattern, and the first adhesion pattern contacts side surfaces of the metal pattern and the second adhesion pattern. The methods may also include forming a second metal structure on the first metal structure. The metal pattern may include a contact portion protruding upwardly beyond an upper surface of the second insulating layer or may include an upper surface recessed with respect to the upper surface of the second insulating layer.

公开(公告)号：US10790278B2

公开(公告)日：2020-09-29

申请号：US16275761

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mingyu Kim ,  Kang-Ill Seo

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/78

Abstract: A semiconductor device including a semiconductor substrate having a recessed top portion and a non-recessed top portion, a first fin protruding upward from a non-recessed top portion with a first thickness, a second fin protruding upward from the recessed top portion with a second thickness greater than the first thickness, a first gate structure on the non-recessed top portion and surrounding the first fin to a first height from the non-recessed top portion, and a second gate structure on the recessed top portion and surrounding the second fin to a second height different from the first height from the recessed top portion may be provided.