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公开(公告)号：US20210075405A1
公开(公告)日：2021-03-11
申请号：US16861903
申请日：2020-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongho SHIN , Kyungtae KANG , Junha LEE , Tongsung KIM , Jangwoo LEE , Jeongdon IHM , Byunghoon JEONG
Abstract: A parameter monitoring circuit includes a code generation circuit configured to generate a first code, to which a first offset is applied, and a second code, to which a second offset is applied; a parameter adjustment circuit configured to generate a first parameter and a second parameter by respectively applying the first code and the second code to a current parameter; a comparator circuit configured to generate a first comparison result and a second comparison result, the first comparison result indicating a comparison result between the first parameter and a reference parameter value, and the second comparison result indicating a comparison result between the second parameter and the reference parameter value; and a parameter error detection circuit configured to detect an error in the current parameter, based on the first comparison result and the second comparison result.
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公开(公告)号：US20210065753A1
公开(公告)日：2021-03-04
申请号：US17012845
申请日：2020-09-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junha LEE , Seonkyoo LEE , Jeongdon IHM , Byunghoon JEONG
IPC: G11C7/10 , H01L25/065 , H01L25/18 , H01L23/00
Abstract: A multi-chip package with reduced calibration time and an impedance control (ZQ) calibration method thereof are provided. A master chip of the multi-chip package performs a first ZQ calibration operation by using a ZQ resistor, and then, the other slave chips simultaneously perform second ZQ calibration operations with respect to data input/output (DQ) pads of the slave chips by using a termination resistance value of a DQ pad of the master chip on the basis of a one-to-one correspondence relationship with the DQ pad of the master chip. The multi-chip package completes ZQ calibration by performing two ZQ calibration operations, thereby decreasing a ZQ calibration time.
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Patent Agency Ranking
公开(公告)号：US20250123776A1
公开(公告)日：2025-04-17
申请号：US18999741
申请日：2024-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin JO , Tongsung KIM , Chiweon YOON , Seonkyoo LEE , Byunghoon JEONG
Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
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公开(公告)号：US20230410855A1
公开(公告)日：2023-12-21
申请号：US18457742
申请日：2023-08-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Taehyeon PARK , Byunghoon JEONG , Chiweon YOON
CPC classification number: G11C7/1012 , G11C7/109 , G11C7/1063 , G11C7/1057 , G11C7/1084 , G11C7/20 , G11C8/06
Abstract: A memory chip, a memory controller, and an operating method of the memory chip are provided. The memory chip includes a plurality of pins; and an interface circuit configured to receive a swap command set from a memory controller through the plurality of pins, obtain a swap command and a swap address from the swap command set, generate a swap enable signal based on the swap command and the swap address, and swap and output a data signal according to the swap enable signal.
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公开(公告)号：US20230138561A1
公开(公告)日：2023-05-04
申请号：US17938214
申请日：2022-10-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongho SHIN , Jungjune PARK , Kyoungtae KANG , Chiweon YOON , Junha LEE , Byunghoon JEONG
Abstract: An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.
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公开(公告)号：US20230127635A1
公开(公告)日：2023-04-27
申请号：US18069685
申请日：2022-12-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byunghoon JEONG , Kyungtae KANG , Jangwoo LEE
IPC: G11C7/22 , G11C7/10 , H03K19/173 , G11C8/18 , G11C29/42
Abstract: A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
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公开(公告)号：US20220229599A1
公开(公告)日：2022-07-21
申请号：US17528285
申请日：2021-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngmin JO , Tongsung KIM , Chiweon YOON , Seonkyoo LEE , Byunghoon JEONG
Abstract: A method of operating a storage device including first and second memory devices and a memory controller, which are connected to a single channel, the method including: transmitting first data output from the first memory device to the memory controller through a data signal line in the single channel; and transmitting a command to the second memory device through the data signal line while the memory controller receives the first data, wherein a voltage level of the data signal line is based on the command and the first data of the first memory device is loaded on the data signal line, and the first data and the command are transmitted in both directions of the data signal line.
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