公开(公告)号：US20130330925A1

公开(公告)日：2013-12-12

申请号：US13893449

申请日：2013-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Hong MIN ,  CHAJEA JO ,  Taeje CHO ,  YOUNG KUN JEE

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/68 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Disclosed are methods of treating a device-substrate, and support-substrates used therein. The methods may include providing the device-substrate having an integrated circuit, bonding a first top surface of the device-substrate to a support-substrate, and polishing a first bottom surface of the device-substrate. The support-substrates include a second top surface, a second bottom surface opposite to the second top surface, and a sidewall connecting the second top and bottom surfaces. Additionally, the support-substrates further include a grooved portion spaced apart from the sidewall and blocking a crack in the support-substrates occurring from the sidewall.

Abstract translation: 公开了处理器件衬底和其中使用的支撑衬底的方法。 所述方法可以包括提供具有集成电路的器件衬底，将器件衬底的第一顶表面接合到支撑衬底，以及抛光器件衬底的第一底表面。 支撑基板包括第二顶表面，与第二顶表面相对的第二底表面和连接第二顶表面和底表面的侧壁。 此外，支撑基板还包括与侧壁间隔开的凹槽部分，并且阻挡从侧壁发生的支撑基板中的裂纹。

公开(公告)号：US20250096047A1

公开(公告)日：2025-03-20

申请号：US18624214

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGSEON KIM ,  DONGKUK LEE ,  CHAJEA JO

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package includes a substrate. A first semiconductor chip is on the substrate and includes a first semiconductor substrate and a plurality of first test pads on a top surface of the first semiconductor substrate. A second semiconductor chip is on the first semiconductor chip and includes a second semiconductor substrate and a second test pad on a bottom surface of the second semiconductor substrate. The first semiconductor chip and the second semiconductor chip are bonded to each other. The plurality of first test pads face the second test pad. The second test pad has a circular ring shape when viewed in plan. The plurality of first test pads are arranged along a circumference of the second test pad. Areas that the plurality of first test pads overlap the second test pad have same sizes as each other.

公开(公告)号：US20220254827A1

公开(公告)日：2022-08-11

申请号：US17731022

申请日：2022-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGHOE CHO ,  CHUNGSUN LEE ,  YOONHA JUNG ,  CHAJEA JO

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48 ,  H01L21/683

Abstract: Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip.

公开(公告)号：US20220122955A1

公开(公告)日：2022-04-21

申请号：US17357378

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： YONGHOE CHO ,  SUNKYOUNG SEO ,  CHAJEA JO

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/538 ,  H01L23/14 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.

公开(公告)号：US20220013501A1

公开(公告)日：2022-01-13

申请号：US17178327

申请日：2021-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： NAMHOON KIM ,  CHAJEA JO ,  Ohguk KWON ,  HYOEUN KIM ,  SEUNGHOON YEON

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US20210202462A1

公开(公告)日：2021-07-01

申请号：US17204225

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JICHUL KIM ,  CHAJEA JO ,  SANG-UK HAN ,  KYOUNG SOON CHO ,  JAE CHOON KIM ,  WOOHYUN PARK

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US20190164942A1

公开(公告)日：2019-05-30

申请号：US16232159

申请日：2018-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNG-KWAN RYU ,  YONGHWAN KWON ,  YUN SEOK CHOI ,  CHAJEA JO ,  TAEJE CHO

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.