公开(公告)号：US20130330925A1

公开(公告)日：2013-12-12

申请号：US13893449

申请日：2013-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Hong MIN ,  CHAJEA JO ,  Taeje CHO ,  YOUNG KUN JEE

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/68 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Disclosed are methods of treating a device-substrate, and support-substrates used therein. The methods may include providing the device-substrate having an integrated circuit, bonding a first top surface of the device-substrate to a support-substrate, and polishing a first bottom surface of the device-substrate. The support-substrates include a second top surface, a second bottom surface opposite to the second top surface, and a sidewall connecting the second top and bottom surfaces. Additionally, the support-substrates further include a grooved portion spaced apart from the sidewall and blocking a crack in the support-substrates occurring from the sidewall.

Abstract translation: 公开了处理器件衬底和其中使用的支撑衬底的方法。 所述方法可以包括提供具有集成电路的器件衬底，将器件衬底的第一顶表面接合到支撑衬底，以及抛光器件衬底的第一底表面。 支撑基板包括第二顶表面，与第二顶表面相对的第二底表面和连接第二顶表面和底表面的侧壁。 此外，支撑基板还包括与侧壁间隔开的凹槽部分，并且阻挡从侧壁发生的支撑基板中的裂纹。

公开(公告)号：US20150093857A1

公开(公告)日：2015-04-02

申请号：US14566685

申请日：2014-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihwan HWANG ,  Young Kun JEE ,  Jung-Hwan KIM ,  Tae Hong MIN ,  Kwang-chul CHOI

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3185 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

Abstract: Provided are semiconductor devices and methods of manufacturing the same. The semiconductor package includes a substrate, a first semiconductor chip mounted on the circuit substrate and having a first width, a second semiconductor chip overlying the first semiconductor chip and having a second width greater than the first width, and a first under filler disposed between the first and second semiconductor chips, covering a side surface of the first semiconductor chip and having an inclined side surface.

Abstract translation: 提供半导体器件及其制造方法。 半导体封装包括基板，安装在电路基板上并具有第一宽度的第一半导体芯片，覆盖第一半导体芯片并且具有大于第一宽度的第二宽度的第二半导体芯片，以及设置在第一半导体芯片 第一和第二半导体芯片，覆盖第一半导体芯片的侧表面并具有倾斜的侧表面。

公开(公告)号：US20140141569A1

公开(公告)日：2014-05-22

申请号：US14018630

申请日：2013-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea JO ,  Ji Hwang KIM ,  Tae Hong MIN ,  Tae-Sub CHANG ,  Taeje CHO

IPC: H01L21/768 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/05552

Abstract: In a method of fabricating a semiconductor device, a first sacrificial through-via is formed to fill a first via-hole extending from a first surface of a first substrate toward a second surface of the first substrate opposite the first surface. The first surface of the first substrate is bonded to a carrier. The first sacrificial through-via is exposed, and the first sacrificial through-via is selectively removed. After selectively removing the first sacrificial through-via, a conductive through-via is formed to fill the first via-hole.

Abstract translation: 在制造半导体器件的方法中，形成第一牺牲通孔以填充从第一衬底的第一表面朝向与第一表面相对的第一衬底的第二表面延伸的第一通孔。 第一衬底的第一表面被结合到载体上。 第一牺牲通孔被暴露，并且选择性地去除第一牺牲通孔。 在选择性地去除第一牺牲通孔之后，形成导电通孔以填充第一通孔。

公开(公告)号：US20140038353A1

公开(公告)日：2014-02-06

申请号：US13955259

申请日：2013-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Tae Hong MIN ,  Chajea JO ,  Taeje CHO ,  Young Kun JEE ,  Yun Seok CHOI

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract translation: 制造半导体封装的方法包括：准备包括彼此横向隔开的封装板部分的母基板，在每个封装板部件上安装包括通孔电极的第一芯片，在母基板上形成第一模层 具有第一芯片，平坦化第一模具层以暴露第一芯片的背面，蚀刻第一芯片的暴露的背面以暴露通孔电极的背面，在平坦化的第一模具层上形成钝化层， 第一芯片的蚀刻背面和通孔电极的背面，并且选择性地去除钝化层以暴露通孔电极的背面。

公开(公告)号：US20200098719A1

公开(公告)日：2020-03-26

申请号：US16438505

申请日：2019-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Sick PARK ,  Un Byoung KANG ,  Tae Hong MIN ,  Teak Hoon LEE ,  Ji Hwan HWANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

公开(公告)号：US20140148007A1

公开(公告)日：2014-05-29

申请号：US14170062

申请日：2014-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Sunpil YOUN ,  Sangwon KIM ,  Kwang-chul CHOI ,  Tae Hong MIN

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a substrate having a first side and a second side such that the first and second sides face each other, a through via plug penetrating the substrate, an insulating film liner, and an antipollution film. The insulating film liner is between the through via plug and the substrate and the insulating film liner has a recessed surface with respect to the second side. The antipollution film covers the second side and the antipollution film is on the recessed surface and between the through via plug and the substrate.

Abstract translation: 半导体器件包括具有第一侧和第二侧的基板，使得第一和第二面彼此面对，贯穿基板的通孔塞，绝缘膜衬垫和防污染膜。 绝缘膜衬垫位于通孔插塞和衬底之间，并且绝缘膜衬套相对于第二侧具有凹陷表面。 防污染膜覆盖第二面，防污染膜位于凹陷表面上，并且在通孔插塞和基底之间。