公开(公告)号：US20160093541A1

公开(公告)日：2016-03-31

申请号：US14714667

申请日：2015-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungduk BAEK ,  Ji Hwang KIM ,  Taeje CHO

IPC: H01L21/66 ,  H01L23/525 ,  H01L21/768 ,  G01R31/26

CPC classification number: H01L22/14 ,  G01R31/2601 ,  H01L22/32 ,  H01L23/5256 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern.

Abstract translation: 制造半导体封装的方法包括提供包括电路图案的半导体芯片，连接焊盘，第一测试焊盘和第二测试焊盘，每个连接焊盘，第一测试焊盘和第二测试焊盘分别电连接到 所述电路图案，通过向所述第一测试焊盘施加第一测试电压和对所述第二测试焊盘施加第二测试电压来评估所述半导体芯片的电特性，所述第二测试电压高于所述第一测试电压，并且电连接所述第二测试电压 测试板从电路图案。

公开(公告)号：US20220130811A1

公开(公告)日：2022-04-28

申请号：US17368028

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeho LEE ,  Taeje CHO

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00

Abstract: A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.

公开(公告)号：US20160314996A1

公开(公告)日：2016-10-27

申请号：US15099926

申请日：2016-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： IL HWAN KIM ,  Sang Hyun BAE ,  HYUEKJAE LEE ,  Taeje CHO ,  Kwang-chul CHOI

IPC: H01L21/67 ,  H01L21/687

CPC classification number: H01L21/67051 ,  B24B7/228

Abstract: The inventive concepts relate to a substrate treating apparatus and a method for treating a substrate using the same. The apparatus includes a spin chuck configured to support a substrate, a grinding head disposed over the spin chuck and configured to grind the substrate supported by the spin chuck, and a nozzle member including a jet nozzle configured to jet high-pressure water to the substrate supported by the spin chuck. The jet nozzle overlaps with the substrate to jet the high-pressure water to an edge of the substrate.

Abstract translation: 本发明的概念涉及基板处理装置和使用其的基板的处理方法。 该装置包括配置成支撑基板的旋转卡盘，设置在旋转卡盘上方并构造成研磨由旋转卡盘支撑的基板的研磨头，以及包括喷射喷嘴的喷嘴构件，该喷嘴构造成将高压水喷射到基板 由旋转卡盘支撑。 喷射喷嘴与基板重叠以将高压水喷射到基板的边缘。

公开(公告)号：US20150069635A1

公开(公告)日：2015-03-12

申请号：US14463650

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun KIM ,  In-Young LEE ,  Chang-Seong JEON ,  Taeje CHO

IPC: H01L25/10 ,  H01L23/34 ,  H01L21/56 ,  H01L23/367 ,  H01L23/31 ,  H01L25/00 ,  H01L23/373

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/345 ,  H01L23/36 ,  H01L23/3677 ,  H01L24/19 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/181 ,  H01L2924/00

Abstract: Provided are semiconductor packages and methods of fabricating the same. The method may include mounting a first semiconductor chip including chip and heat-transfer regions and a lower heat-transfer pattern disposed on the heat-transfer region, on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to enclose the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat-transfer pattern, forming a heat-pathway pattern in the opening, and forming a heat-dissipating part on the second semiconductor chip and the mold layer to be connected to the heat-pathway pattern.

Abstract translation: 提供半导体封装及其制造方法。 该方法可以包括在基板上安装包括芯片和传热区域的第一半导体芯片和设置在传热区域上的较低传热图案，将第二半导体芯片安装在第一半导体芯片的芯片区域上， 在所述基板上形成模具层以包围所述第一和第二半导体芯片，在所述模具层中形成开口以露出所述下部传热图案的至少一部分，以在所述开口中形成热通路图案，并且形成 第二半导体芯片上的散热部件和要连接到热通路图案的模具层。

公开(公告)号：US20160372447A1

公开(公告)日：2016-12-22

申请号：US15250951

申请日：2016-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-young JANG ,  Chang-Seong JEON ,  CHAJEA JO ,  Taeje CHO

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1412 ,  H01L2224/1413 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/321 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83379 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.

公开(公告)号：US20150140785A1

公开(公告)日：2015-05-21

申请号：US14488883

申请日：2014-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Soo KWAK ,  Youngsu KIM ,  Sangwook PARK ,  Taeje CHO

IPC: H01L21/78 ,  H01L23/544 ,  H01L21/683 ,  H01L21/02 ,  H01L21/268

CPC classification number: H01L21/78 ,  H01L21/02013 ,  H01L21/268 ,  H01L21/6835 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device include preparing an initial substrate including an edge region and a central region in which circuit patterns are formed, forming a reforming region in the edge region of the initial substrate, grinding the initial substrate to form a substrate, and cutting the substrate to form a semiconductor chip including each of the circuit patterns. A crystal structure of the reforming region is different from that of the initial substrate.

Abstract translation: 制造半导体器件的方法包括制备包括边缘区域和形成电路图案的中心区域的初始衬底，在初始衬底的边缘区域中形成重整区域，研磨初始衬底以形成衬底，以及 切割基板以形成包括每个电路图案的半导体芯片。 重整区域的晶体结构与初始衬底的晶体结构不同。

公开(公告)号：US20130330925A1

公开(公告)日：2013-12-12

申请号：US13893449

申请日：2013-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Hong MIN ,  CHAJEA JO ,  Taeje CHO ,  YOUNG KUN JEE

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/68 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/056 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

Abstract: Disclosed are methods of treating a device-substrate, and support-substrates used therein. The methods may include providing the device-substrate having an integrated circuit, bonding a first top surface of the device-substrate to a support-substrate, and polishing a first bottom surface of the device-substrate. The support-substrates include a second top surface, a second bottom surface opposite to the second top surface, and a sidewall connecting the second top and bottom surfaces. Additionally, the support-substrates further include a grooved portion spaced apart from the sidewall and blocking a crack in the support-substrates occurring from the sidewall.

Abstract translation: 公开了处理器件衬底和其中使用的支撑衬底的方法。 所述方法可以包括提供具有集成电路的器件衬底，将器件衬底的第一顶表面接合到支撑衬底，以及抛光器件衬底的第一底表面。 支撑基板包括第二顶表面，与第二顶表面相对的第二底表面和连接第二顶表面和底表面的侧壁。 此外，支撑基板还包括与侧壁间隔开的凹槽部分，并且阻挡从侧壁发生的支撑基板中的裂纹。

公开(公告)号：US20240203969A1

公开(公告)日：2024-06-20

申请号：US18418964

申请日：2024-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeho LEE ,  Taeje CHO

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08146 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.

公开(公告)号：US20170110388A1

公开(公告)日：2017-04-20

申请号：US15290899

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon PARK ,  Won Il LEE ,  Chajea JO ,  Taeje CHO

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L23/13 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13117 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/01058 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.

公开(公告)号：US20150318261A1

公开(公告)日：2015-11-05

申请号：US14611585

申请日：2015-02-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo CHUNG ,  InYoung LEE ,  Taeje CHO

IPC: H01L25/065 ,  H01L21/306 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/29 ,  H01L21/768 ,  H01L21/304

CPC classification number: H01L25/50 ,  H01L21/3043 ,  H01L21/30604 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/00 ,  H01L23/29 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3178 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/03 ,  H01L24/08 ,  H01L24/89 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/92125 ,  H01L2224/92152 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/83

Abstract: The method of fabricating a semiconductor package including preparing a semiconductor wafer having a first side and a second side, the second side facing the first side, and the semiconductor wafer including a through via exposed through the first side, forming trenches at cutting areas between chip areas and at edge areas of the semiconductor wafer on the first side, stacking a semiconductor chip on the through via, forming an under fill resin layer to fill a gap between the semiconductor chip and the semiconductor wafer and to cover a side of the semiconductor chip, and forming a molding layer to cover at least a portion of the under fill resin layer and to fill at least a portion of the respective trenches may be provided.

Abstract translation: 一种制造半导体封装的方法，包括制备具有第一侧和第二侧的半导体晶片，面向第一侧的第二面，以及包括通过第一侧露出的通孔的半导体晶片，在芯片之间的切割区域处形成沟槽 区域和第一侧的半导体晶片的边缘区域，在通孔上堆叠半导体芯片，形成下填充树脂层以填充半导体芯片和半导体晶片之间的间隙并覆盖半导体芯片的一侧 并且可以提供形成模制层以覆盖下填充树脂层的至少一部分并填充相应沟槽的至少一部分。