公开(公告)号：US20250022828A1

公开(公告)日：2025-01-16

申请号：US18609921

申请日：2024-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Haksun Lee ,  Dohyun Kim ,  Sunkyoung Seo ,  Chajea Jo

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00

Abstract: The present disclosure relates to semiconductor packages and methods of fabricating the semiconductor packages. An example semiconductor package includes a first semiconductor die including a first substrate and a first bonding layer on the first substrate, a second semiconductor die disposed on the first semiconductor die, the second semiconductor die including a second substrate and a second bonding layer under the second substrate, and a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die, where at least one pore is disposed in the silicon oxide layer, and the at least one pore has a height of 1 Å to 2 nm.

公开(公告)号：US11923342B2

公开(公告)日：2024-03-05

申请号：US17705872

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Han ,  Chajea Jo ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/13

Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

公开(公告)号：US11600608B2

公开(公告)日：2023-03-07

申请号：US17204225

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichul Kim ,  Chajea Jo ,  Sang-Uk Han ,  Kyoung Soon Cho ,  Jae Choon Kim ,  Woohyun Park

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/18

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US11545512B2

公开(公告)日：2023-01-03

申请号：US17154890

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Ohguk Kwon ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L27/146 ,  H04N5/225

Abstract: An image sensor package comprises: an image sensor chip configured to convert light collected from an outside thereof into an electrical signal; a package substrate disposed under the image sensor chip the package substrate configured to process the electrical signal converted from the image sensor chip; a glass substrate disposed over the image sensor chip while being spaced apart from the image sensor chip; a seal pattern disposed between an upper surface of the package substrate and a lower surface of the glass substrate while surrounding the image sensor chip; and a protection pattern disposed on the package substrate outside the seal pattern, the protection pattern comprising a single-component material, wherein the seal pattern comprises a material different from the material of the protection pattern.

公开(公告)号：US10985152B2

公开(公告)日：2021-04-20

申请号：US16503121

申请日：2019-07-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jichul Kim ,  Chajea Jo ,  Sang-Uk Han ,  Kyoung Soon Cho ,  Jae Choon Kim ,  Woohyun Park

IPC: H01L25/18 ,  H01L27/146 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/18

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a second semiconductor chip on the substrate and spaced apart from the first semiconductor device, a mold layer on the substrate and covering sides of the first and second semiconductor chips, and an image sensor unit on the first and second semiconductor chips and the mold layer. The image sensor unit is electrically connected to the first semiconductor chip.

公开(公告)号：US10651224B2

公开(公告)日：2020-05-12

申请号：US16058451

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Chajea Jo ,  Hyoeun Kim ,  Jongbo Shim ,  Sang-uk Han

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.

公开(公告)号：US10121731B2

公开(公告)日：2018-11-06

申请号：US15290899

申请日：2016-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Cheon Park ,  Won Il Lee ,  Chajea Jo ,  Taeje Cho

IPC: H01L23/48 ,  H01L23/13 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.

公开(公告)号：US20250096208A1

公开(公告)日：2025-03-20

申请号：US18674004

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongoh HA ,  Juhyeon Kim ,  Chajea Jo

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor chip having first and second surfaces opposing each other; first lower electrode pads on the first surface; a first insulating layer surrounding a side surface of each of the first lower electrode pads on the first surface; through-electrodes penetrating through at least a portion of the first semiconductor chip; first upper electrode pads on the through-electrodes; a first dielectric layer covering at least a portion of each of the first insulating layer, the first semiconductor chip, the through-electrodes, and the first upper electrode pads on the through-electrodes; where the first dielectric layer comprises a first portion and a second portion on the first portion of the first dielectric layer, and a first outer surface of the first portion is located on an inner side closer to the first semiconductor chip than a second outer surface of the second portion.

公开(公告)号：US20240194575A1

公开(公告)日：2024-06-13

申请号：US18380042

申请日：2023-10-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryong Oh ,  Chajea Jo

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/08146 ,  H01L2224/08168 ,  H01L2224/16147 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/182

Abstract: A semiconductor package includes a first semiconductor chip including a first bonding layer, the first bonding layer including a first chip pad and a first insulating layer covering a side surface of the first chip pad, a second semiconductor chip disposed below the first semiconductor chip and including a substrate having front and rear surfaces, the front surface forming a second bonding layer, and through-electrodes passing through the substrate and having protrusions protruding from the rear surface, the second bonding layer including a second chip pad contacting the first chip pad and a second insulating layer covering a side surface of the second chip pad, a redistribution layer disposed below the second semiconductor chip and electrically connected to the second semiconductor chip, vias disposed between the redistribution layer and the first semiconductor chip and disposed around the second semiconductor chip, and an encapsulant surrounding the second semiconductor chip, the redistribution layer, and the vias. The encapsulant may be in contact with the protrusions of the through-electrodes.

公开(公告)号：US11942446B2

公开(公告)日：2024-03-26

申请号：US17165429

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Sunkyoung Seo ,  Seunghoon Yeon ,  Chajea Jo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L2224/14181

Abstract: A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.