公开(公告)号：US20250004370A1

公开(公告)日：2025-01-02

申请号：US18392365

申请日：2023-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Beomseok KIM ,  Minsang KIM ,  Haengdeog KOH ,  Yoonhyun KWAK ,  Chanjae AHN ,  Changheon LEE ,  Kyuhyun IM ,  Sungwon CHOI

IPC: G03F7/038 ,  C08F12/22 ,  G03F7/004 ,  G03F7/20

Abstract: Provided are a polymer including a first repeating unit represented by Formula 1, a resist composition including the polymer, and a method of forming a pattern using the resist composition: wherein descriptions of L11 to L14, a11 to a13, A11, X11, R11, R12, b12 and p in Formula 1 are provided in the present specification.

公开(公告)号：US20240038510A1

公开(公告)日：2024-02-01

申请号：US18469208

申请日：2023-09-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changheon LEE ,  Sangki NAM ,  Taesun SHIN

IPC: H01J37/32 ,  H01L21/3065 ,  H01L21/67

CPC classification number: H01J37/32834 ,  H01L21/3065 ,  H01L21/67069 ,  H01J37/3244 ,  H01J37/32091 ,  H01J37/32642 ,  H01J37/32743 ,  H01J37/32568 ,  H01J37/3211 ,  H01J2237/334

Abstract: A substrate processing method includes inserting a substrate from an outside into a processing space, supplying a process gas from a gas supply unit to the processing space, producing plasma based on the process gas, performing an etching process for the substrate using ions included in the plasma, and discharging a processed gas produced in the etching process through a discharge part. The discharge part includes a first slit extending through a flange part, and a second slit connected to the first slit while extending through a side wall part connected to the flange part. A vertical length of the first slit is equal to a vertical length of the second slit. A horizontal length of the first slit is about 5 times to about 7 times the vertical length of the first slit.

公开(公告)号：US20220406808A1

公开(公告)日：2022-12-22

申请号：US17724002

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Nakjin SON ,  Jeongeun KIM ,  Juseong MIN ,  Changheon LEE

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.