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    METHOD AND APPARATUS FOR PREVENTING BANK CONFLICT IN MEMORY
    14.
    发明申请
    METHOD AND APPARATUS FOR PREVENTING BANK CONFLICT IN MEMORY 审中-公开
    用于防止存储器中的银行冲突的方法和装置

    公开(公告)号：US20170068620A1

    公开(公告)日：2017-03-09

    申请号：US15121999

    申请日：2015-02-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Won-Sub KIM ,  Tai-song JIN ,  Do-hyung KIM ,  Seung-won LEE

    IPC: G06F12/0844 ,  G06F9/48 ,  G06F13/16 ,  G06F9/52

    CPC classification number: G06F12/0844 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/4831 ,  G06F9/52 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/372 ,  G06F13/376 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2212/608

    Abstract: A method of preventing a bank conflict in a memory includes determining processing timing of each of threads of function units to access a first memory bank in which occurrence of a bank conflict is expected, setting a variable latency of each of the threads for sequential access of the threads according to the determined processing timing, sequentially storing the threads in a data memory queue according to the determined processing timing, and performing an operation by allowing the threads stored in the data memory queue to sequentially access the first memory bank whenever the variable latency of each of the threads passes.

    Abstract translation: 一种防止存储器中的存储体冲突的方法包括：确定功能单元的每个线程的处理定时，以访问预期发生存储体冲突的第一存储体，设置每个线程的可变等待时间以顺序访问 根据所确定的处理定时，线程根据所确定的处理定时顺序地将线程存储在数据存储器队列中，并且通过允许存储在数据存储器队列中的线程在可变延迟时间内顺序地存取第一存储体，执行操作 的每个线程通过。

    DIRECT MEMORY ACCESS CONTROLLER AND SYSTEM FOR ACCESSING CHANNEL BUFFER
    16.
    发明申请
    DIRECT MEMORY ACCESS CONTROLLER AND SYSTEM FOR ACCESSING CHANNEL BUFFER 审中-公开
    直接存储器访问控制器和用于访问通道缓冲器的系统

    公开(公告)号：US20150227479A1

    公开(公告)日：2015-08-13

    申请号：US14619783

    申请日：2015-02-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ki-seok KWON ,  Suk-jin KIM ,  Do-hyung KIM

    IPC: G06F13/28

    CPC classification number: G06F13/28 ,  Y02D10/14

    Abstract: A direct memory access (DMA) controller is provided. The DMA controller includes a processor interface configured to directly receive information representing a first operation sent by a processor to a buffer, and transmit data corresponding to the first operation stored in the buffer to the processor core or record data corresponding to the first operation in the buffer, and a buffer group connected to the processor interface, and including a plurality of buffers.

    Abstract translation: 提供直接存储器访问（DMA）控制器。 DMA控制器包括：处理器接口，被配置为直接接收表示由处理器发送到缓冲器的第一操作的信息，并将对应于缓冲器中存储的第一操作的数据发送到处理器核心，或者记录对应于第一操作的数据 缓冲器和连接到处理器接口的缓冲器组，并且包括多个缓冲器。

    IMAGE PROCESSING APPARATUS AND METHOD
    17.
    发明申请
    IMAGE PROCESSING APPARATUS AND METHOD 有权
    图像处理装置和方法

    公开(公告)号：US20150116338A1

    公开(公告)日：2015-04-30

    申请号：US14525856

    申请日：2014-10-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-uk CHO ,  Young-su MOON ,  Jong-hun LEE ,  Yong-min TAI ,  Do-hyung KIM ,  Si-hwa LEE

    IPC: G06T1/20

    CPC classification number: G06F15/8053 ,  G06F9/3895 ,  G06T1/60 ,  G09G5/363 ,  G09G5/39

    Abstract: Disclosed are an image processing apparatus and method that more efficiently process image data. The image processing apparatus includes a vector data manager that receives at least some of all image data and converts the received image data into vector data, a vector processor that receives the vector data from the vector data manager, performs a vector processing operation by using the vector data, and generates output vector data as a result of the vector processing operation, and a synchronizer that controls a timing of when the vector data manager transmits the vector data to the vector processor.

    Abstract translation: 公开了一种更有效地处理图像数据的图像处理装置和方法。 图像处理装置包括：矢量数据管理器，其接收所有图像数据中的至少一部分，并将接收到的图像数据转换为矢量数据;从矢量数据管理器接收矢量数据的矢量处理器，通过使用 矢量数据，并且作为矢量处理操作的结果生成输出矢量数据，以及控制矢量数据管理器向矢量处理器发送矢量数据时的定时的同步器。

    METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA
    19.
    发明申请
    METHOD OF COMPRESSING AND RESTORING CONFIGURATION DATA 有权
    压缩和恢复配置数据的方法

    公开(公告)号：US20150280740A1

    公开(公告)日：2015-10-01

    申请号：US14671377

    申请日：2015-03-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young-chul CHO ,  Do-hyung KIM ,  Suk-jin KIM ,  Si-hwa LEE

    IPC: H03M7/42

    CPC classification number: H03M7/60 ,  H03M7/30

    Abstract: A method of compressing configuration data used in a reconfigurable processor including generating one piece of combined data by combining configuration data used at two or more cycles and generating a bit table indicating valid operations at each of the two or more cycles among operations included in the combined data

    Abstract translation: 一种压缩在可重构处理器中使用的配置数据的方法，包括通过组合在两个或多个周期中使用的配置数据来生成一个组合数据，并且生成指示在组合中包括的操作中的两个或更多个周期中的每一个的有效操作的位表 数据

    METHOD AND APPARATUS FOR MANAGING REGISTER PORT
    20.
    发明申请
    METHOD AND APPARATUS FOR MANAGING REGISTER PORT 有权
    管理注册港的方法和装置

    公开(公告)号：US20150261695A1

    公开(公告)日：2015-09-17

    申请号：US14644951

    申请日：2015-03-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Tai-Song JIN ,  Jae-Un PARK ,  Do-hyung KIM ,  Seung-won LEE

    IPC: G06F13/10 ,  G06F1/32

    CPC classification number: G06F13/102 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    Abstract: Provided is a method of managing a register port, the method including performing scheduling on register ports that are used during a plurality of cycles to enable performing of a calculation; encoding data of the register ports according to results of the scheduling, the encoding of the data including, with respect to data of one of the register ports that does not have a schedule during one of the plurality of cycles, equally encoding the data of the one register port during the one cycle with data of an adjacent cycle of the one register port, the adjacent cycle being adjacent to the one cycle; and transmitting results of the encoding to a device that includes the register ports.

    Abstract translation: 提供了一种管理寄存器端口的方法，该方法包括对在多个周期期间使用的寄存器端口执行调度以使得能够执行计算; 根据调度结果对寄存器端口的数据进行编码，对于在多个周期中的一个周期期间不具有调度的寄存器端口之一的数据，数据的编码同样对 在一个周期内一个寄存器端口与一个寄存器端口的相邻周期的数据相邻，相邻周期与该周期相邻; 以及将所述编码的结果发送到包括所述寄存器端口的设备。

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