公开(公告)号：US20250079154A1

公开(公告)日：2025-03-06

申请号：US18652323

申请日：2024-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonyoung Kim ,  Dohyun Kim ,  Sechan Kim ,  Kijong Park ,  Yuri Park ,  Sunjoong Song ,  Eunjin Song ,  Seungmin Shin ,  Seungcheol Chae ,  Sangjoon Park ,  Hyunjin Jang

IPC: H01L21/02 ,  H01L21/311

Abstract: A method of manufacturing an integrated circuit device includes forming a hafnium oxide film on a substrate and partially etching the hafnium oxide film. Partially etching the hafnium oxide film includes performing a dry treatment that changes components of a surface region that extends from an exposed surface of the hafnium oxide film into the hafnium oxide film by as much as a predetermined thickness by isotropically exposing the hafnium oxide film to a gas mixture that includes a halogen element-containing gas and a catalytic gas that includes hydrogen atoms in an atmosphere in which no plasma is applied onto the substrate, performing a wet treatment with an acidic solution that at least partially removes the component-changed surface region from the hafnium oxide film, and repeating a sequence of the dry treatment and the wet treatment.

公开(公告)号：US20240170464A1

公开(公告)日：2024-05-23

申请号：US18356325

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Dohyun Kim ,  SeungRyong Oh

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/08148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2924/15174

Abstract: Disclosed is a semiconductor package including a substrate, a first semiconductor chip on the substrate and including a through via in the first semiconductor chip and a plurality of first bonding pads on an upper portion of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a plurality of second bonding pads on a lower portion of the second semiconductor chip, and a conductive post between a top surface of the substrate and a bottom surface of the second semiconductor chip and laterally spaced apart from the first semiconductor chip. The first bonding pads are in contact with the second bonding pads. A width in a first direction parallel to a plane defined by a bottom surface of the substrate of the second semiconductor chip is greater than a width in the first direction of the first semiconductor chip.

公开(公告)号：US20240055406A1

公开(公告)日：2024-02-15

申请号：US18364802

申请日：2023-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongseon Kim ,  Dohyun Kim ,  Juhyeon Kim ,  Hyoeun Kim ,  Seonkyung Seo ,  Chajea Jo

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L25/105 ,  H01L23/3107 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2224/0384 ,  H01L2224/039 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05541 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/08235 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/38

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.