公开(公告)号：US11488953B2

公开(公告)日：2022-11-01

申请号：US17036355

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Seok Ha ,  Hyun Seung Song ,  Hyo Jin Kim ,  Kyoung Mi Park ,  Guk Il An

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

公开(公告)号：US20220069128A1

公开(公告)日：2022-03-03

申请号：US17518741

申请日：2021-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Hyo Jin Kim ,  Dae Won Ha

IPC: H01L29/78 ,  H01L21/762

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

公开(公告)号：US10825809B2

公开(公告)日：2020-11-03

申请号：US16290199

申请日：2019-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Seok Ha ,  Hyun Seung Song ,  Hyo Jin Kim ,  Kyoung Mi Park ,  Guk Il An

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/66 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

公开(公告)号：US10304819B2

公开(公告)日：2019-05-28

申请号：US15838840

申请日：2017-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin Kim ,  Kwan Young Chun

IPC: H01L27/02 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device includes a cell region that includes a first active region and a second active region extending in a first direction and a separation region between the first active region and the second active region. The cell region has a first width. A first gate structure and a second gate structure are disposed on the cell region, are spaced apart from each other in the first direction, and extend in the second direction. A first metal line and a second metal line are disposed on the cell region, extend in the first direction, and are spaced apart from each other by a first pitch. Each of the first and second metal lines has a second width. A first gate contact electrically connects the first gate structure and the first metal line. At least a portion of the first gate contact overlaps the separation region. A second gate contact electrically connects the second gate structure and the second metal line. At least a portion of the second gate contact overlaps the separation region. The first width divided by a sum of the first pitch and the second width is six or less.

公开(公告)号：US10243045B2

公开(公告)日：2019-03-26

申请号：US15800483

申请日：2017-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan Yu ,  Hyo Jin Kim ,  Ryong Ha

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/762

Abstract: A semiconductor device is provided. The semiconductor device includes a fin-type pattern formed on a substrate and including first and second sidewalls, which are defined by a trench, a field insulating film placed in contact with the first and second sidewalls and filling the trench, and an epitaxial pattern formed on the fin-type pattern and including a first epitaxial layer and a second epitaxial layer, which is formed on the first epitaxial layer.

公开(公告)号：US20180358346A1

公开(公告)日：2018-12-13

申请号：US15838840

申请日：2017-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin Kim ,  KWAN YOUNG CHUN

IPC: H01L27/02 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0207 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681

Abstract: A semiconductor device includes a cell region that includes a first active region and a second active region extending in a first direction and a separation region between the first active region and the second active region. The cell region has a first width. A first gate structure and a second gate structure are disposed on the cell region, are spaced apart from each other in the first direction, and extend in the second direction. A first metal line and a second metal line are disposed on the cell region, extend in the first direction, and are spaced apart from each other by a first pitch. Each of the first and second metal lines has a second width. A first gate contact electrically connects the first gate structure and the first metal line. At least a portion of the first gate contact overlaps the separation region. A second gate contact electrically connects the second gate structure and the second metal line. At least a portion of the second gate contact overlaps the separation region. The first width divided by a sum of the first pitch and the second width is six or less.

公开(公告)号：US20250006792A1

公开(公告)日：2025-01-02

申请号：US18411313

申请日：2024-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Hyun Ryu ,  Dong Hoon Hwang ,  Myung Il Kang ,  Hyo Jin Kim ,  Byung Ho Moon ,  Nam Hyun Lee

IPC: H01L29/10 ,  H01L29/417

Abstract: A semiconductor device includes a first and second channel separation structures extending in a first direction and spaced apart from each other in a second direction, first gate structures spaced apart from each other in the first direction between the first and second channel separation structures and in contact with the first and second channel separation structures, first and second channel patterns including first and second sheet patterns, respectively, spaced apart from each other in a third direction and in contact with the corresponding first and second channel separation structures, first and second source/drain patterns between the first and second channel separation structures, the first source/drain patterns in contact with the first channel patterns and the first channel separation structure, the second source/drain patterns in contact with the second channel patterns and the second channel separation structure, and first gate separation structures between the first and second source/drain patterns.

公开(公告)号：US20240363712A1

公开(公告)日：2024-10-31

申请号：US18505279

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Moon Lee ,  Jin Bum Kim ,  Hyo Jin Kim ,  Yong Jun Nam ,  In Geon Hwang

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate, an active pattern extended in a first horizontal direction on the substrate, a plurality of nanosheets stacked and spaced apart from each other in a vertical direction on the active pattern, a gate electrode extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern, a gate insulating layer between the plurality of nanosheets and the gate electrode, and a doping layer between the plurality of nanosheets and the gate insulating layer, the doping layer including silicon (Si) or silicon germanium (SiGe) and doped with a doping material, at least a portion of the doping layer overlapping an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.

公开(公告)号：US11728430B2

公开(公告)日：2023-08-15

申请号：US17518741

申请日：2021-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Hyo Jin Kim ,  Dae Won Ha

IPC: H01L29/78 ,  H01L21/762

CPC classification number: H01L29/7849 ,  H01L21/76224 ,  H01L29/785

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

公开(公告)号：US10185798B2

公开(公告)日：2019-01-22

申请号：US15343860

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin Kim ,  Su Hyeon Kim ,  Azmat Raheel ,  Chul Hong Park

IPC: G06F17/50 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided. The fabricating method of a semiconductor device includes loading a first layout, wherein the first layout comprises a first active region and a first dummy region, and the first active region comprises a fin-type pattern design having a first width, generating a second layout by substituting the fin-type pattern design with a nanowire structure design and forming a nanowire structure by using the second layout, wherein the second layout comprises a second active region in the same size as the first active region, and a second dummy region in the same size as the first dummy region, the nanowire structure design has a second width greater than the first width, and the nanowire structure comprises a first nanowire extending in a first direction, a second nanowire extending in the first direction and being formed on the first nanowire at a spacing apart from the first nanowire, a gate electrode surrounding a periphery of the first nanowire and extending in a second direction of intersecting with the first direction, a gate spacer being formed on a sidewall of the gate electrode and comprising an inner sidewall and an outer sidewall facing each other, the inner sidewall of the gate spacer facing a side surface of the gate electrode, and a source/drain epitaxial layer on at least one side of the gate electrode and being connected to the first nanowire.