公开(公告)号：US09634024B2

公开(公告)日：2017-04-25

申请号：US14642086

申请日：2015-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Chung-Jin Kim ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee ,  Moo-Rym Choi

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.

公开(公告)号：US11776631B2

公开(公告)日：2023-10-03

申请号：US17357494

申请日：2021-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Gn Yun ,  Jae-Duk Lee

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483

Abstract: An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.

公开(公告)号：US11728220B2

公开(公告)日：2023-08-15

申请号：US17510500

申请日：2021-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Jae-Duk Lee ,  Jai-Hyuk Song

IPC: H01L21/8234 ,  G11C5/06 ,  H01L23/522 ,  H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/30 ,  H10B43/35 ,  H01L21/8232 ,  H01L21/822

CPC classification number: H01L21/823462 ,  G11C5/063 ,  H01L21/8221 ,  H01L21/8232 ,  H01L21/823487 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35

Abstract: Integrated circuit devices may include a plurality of word line structures and a plurality of insulating films that are stacked alternately. Sides of the plurality of word line structures and the plurality of insulating films define a side of a channel hole extending through the plurality of word line structures and the plurality of insulating films. The devices may also include a blocking dielectric film on the side of the channel hole, and a plurality of charge storage films on the blocking dielectric film and on the sides of the plurality of word line structures, respectively. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film sequentially stacked on a respective one of the sides of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

公开(公告)号：US10026611B2

公开(公告)日：2018-07-17

申请号：US15590926

申请日：2017-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Duk Lee ,  Young-Woo Park

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11568 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

公开(公告)号：US09905568B2

公开(公告)日：2018-02-27

申请号：US15251580

申请日：2016-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-Hoon Son ,  Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Duk Lee ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833

Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

公开(公告)号：US09508738B2

公开(公告)日：2016-11-29

申请号：US14591929

申请日：2015-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Duk Lee ,  Young-Woo Park

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L21/02636 ,  H01L21/28282 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

Abstract translation: 半导体器件包括下绝缘层，在下绝缘层上彼此分离的多个基底层图案，在基底层图案之间的分离层图案，在垂直方向上延伸的多个通道相对于 基底层图案和围绕通道的外侧壁的多条栅极线在垂直方向上堆叠并彼此间隔开。