公开(公告)号：US12256566B2

公开(公告)日：2025-03-18

申请号：US17714450

申请日：2022-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim

IPC: H10D64/23 ,  H10D30/01 ,  H10D30/67 ,  H10D64/01

Abstract: A semiconductor device includes an active pattern on a substrate, source/drain patterns on the active pattern, a plurality of channel layers stacked on the active pattern to be vertically spaced apart from each other and connecting the source/drain patterns with each other, a gate electrode between the source/drain patterns to cross the active pattern and to surround the channel layers, and active contacts at opposite sides of the gate electrode to cover top surfaces of the source/drain patterns. A width of each of the active contacts is smaller than or equal to the largest width of each of the source/drain patterns. Each of the top surfaces of the source/drain patterns has an inclined surface that is inclined relative to a top surface of the substrate, and each of the active contacts includes a protruding portion that protrudes toward the inclined surface.

公开(公告)号：US12256564B2

公开(公告)日：2025-03-18

申请号：US18415765

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H10D62/13 ,  H10D30/60 ,  H10D30/67 ,  H10D30/69 ,  H10D62/822 ,  H10D64/01 ,  H10D64/23 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D84/90

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US12178034B2

公开(公告)日：2024-12-24

申请号：US18501576

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil Lee ,  Youngjun Kim ,  Jinbum Kim

IPC: H10B12/00

Abstract: A semiconductor device including an active pattern; a gate structure connected to the active pattern; a bit line structure connected to the active pattern; a buried contact connected to the active pattern; a contact pattern covering the buried contact; a landing pad connected to the contact pattern; and a capacitor structure connected to the landing pad, wherein the buried contact includes a first growth portion and a second growth portion spaced apart from each other, and the landing pad includes an interposition portion between the first growth portion and the second growth portion.

公开(公告)号：US20240321991A1

公开(公告)日：2024-09-26

申请号：US18503019

申请日：2023-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ingeon Hwang ,  Jinbum Kim ,  Hyojin Kim ,  Sangmoon Lee ,  Yongjun Nam ,  Taehyung Lee

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a fin-type active region on a substrate, a nanosheet on a fin top surface of the fin-type active region, the nanosheet being apart from the fin top surface of the fin-type active region in a vertical direction, a gate line surrounding the nanosheet on the fin-type active region, and a source/drain region on the fin-type active region, the source/drain region being in contact with the nanosheet, wherein the nanosheet includes a multilayered sheet comprising a first outer semiconductor sheet, a core semiconductor sheet, and a second outer semiconductor sheet, which are sequentially stacked in the vertical direction.

公开(公告)号：US12046682B2

公开(公告)日：2024-07-23

申请号：US17689322

申请日：2022-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ingyu Jang ,  Jinbum Kim ,  Dahye Kim ,  Sujin Jung ,  Dongsuk Shin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/764 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/78696 ,  H01L21/0259 ,  H01L21/764 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.

公开(公告)号：US20230411458A1

公开(公告)日：2023-12-21

申请号：US18239660

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ilgyou Shin ,  Minyi Kim ,  Myung Gil Kang ,  Jinbum Kim ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/785

Abstract: A semiconductor device includes; a substrate including a first region and a second region, a first active pattern extending upward from the first region, a first superlattice pattern on the first active pattern, a first active fin centrally disposed on the first active pattern, a first gate electrode disposed on the first active fin, and first source/drain patterns disposed on opposing sides of the first active fin and on the first active pattern. The first superlattice pattern includes at least one first semiconductor layer and at least one first blocker-containing layer, and the first blocker-containing layer includes at least one of oxygen, carbon, fluorine and nitrogen.

公开(公告)号：US20230395684A1

公开(公告)日：2023-12-07

申请号：US18130070

申请日：2023-04-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sujin JUNG ,  Jinbum Kim ,  Dahye Kim ,  Ingyu Jang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region extending in a first direction on a substrate, a plurality of channel layers spaced apart from each other in a vertical direction, a gate structure enclosing the plurality of channel layers, respectively, and a source/drain region contacting the plurality of channel layers. The source/drain region includes a first epitaxial layer extending to contact the plurality of channel layers, and a second epitaxial layer on the first epitaxial layer. A surface in which the first epitaxial layer and the second epitaxial layer contact each other includes: first surfaces having a first slope; second surfaces having a second slope, different from the first slope; first bent portions between the first surfaces and the second surfaces; and a second bent portion in which the second surfaces meet.

公开(公告)号：US20230361215A1

公开(公告)日：2023-11-09

申请号：US18133730

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Daehong Ko ,  Jinbum Kim ,  Sangmoon Lee ,  Daeseop Byeon ,  Seran Park ,  Hyunsu Shin ,  Kiseok Lee ,  Chunghee Jo

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/6656

Abstract: A semiconductor device including a substrate extending in a first direction and a second direction perpendicular to the first direction, a first active pattern protruding from a top surface of the substrate and extending in the first direction, an isolation pattern covering a sidewall of the first active pattern on the substrate, first silicon patterns spaced apart from each other in a third direction on the first active pattern, the third direction perpendicular to the first direction and second direction, a first source/drain layer extending in the third direction from a top surface of the first active pattern on the first active pattern, and in contact with sidewalls of the first silicon patterns, wherein a sidewall of the first source/drain layer in the second direction has a constant inclination with respect to the top surface of the substrate, and a gate structure extending in the second direction while filling a gap between the first silicon patterns on the substrate.

公开(公告)号：US11417731B2

公开(公告)日：2022-08-16

申请号：US17128153

申请日：2020-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US20220068920A1

公开(公告)日：2022-03-03

申请号：US17524128

申请日：2021-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762

Abstract: Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.