Abstract:
Provided are a memory device and a memory controller, which are configured to repair a weak word line, and a method of operating a storage device including the memory device and the memory controller. A memory device includes a memory cell array including a plurality of normal word lines and at least one spare word line, and a repair controller configured to set memory cells connected to at least one weak word line to a first operation mode and further configured to set memory cells connected to the at least one spare word line to a second operation mode. The at least one weak word line is detected from among the normal word lines based on a test result.
Abstract:
An operating method of a memory controller configured to control a memory device including memory blocks each for storing a plurality of pages is provided. The operating method includes transferring a program command to the memory device based on a write request from a host, updating a valid page bitmap representing validity of a plurality of pages based on valid page information received from the memory device, calculating a fragmentation ratio representing a segmentation degree between at least one valid page and at least one invalid page of a memory block based on the valid page bitmap, determining source blocks among the memory blocks in ascending order of fragmentation ratios, and performing garbage collection on the source blocks.
Abstract:
A method and system for providing power saving for wired connected devices. The method includes determining a power saving mode by one or more of a first communication device and a second communication device based on one or more of a video content state and one or more un-allocated communication paths. A power saving operation is performed while using a wired link between the first communication device and the second communication device based on the determined power saving mode.
Abstract:
A method of controlling a physical quantity of a semiconductor manufacturing facility includes performing feedforward control including control of a first stage feedforward to accelerate a physical quantity control system to a physical limit performance and control of a second stage feedforward to reduce acceleration of the physical quantity control system at a first switching point, switching the feedforward control to feedback control at a second switching point, and performing feedback control on the physical quantity control system.
Abstract:
A memory package includes; a first memory chip including first memory pads, and a buffer chip including first buffer pads respectively connected with the first memory pads and second buffer pads connected with an external device. The buffer chip respectively communicates signals received via the second buffer pads to the first buffer pads in response to a swap enable signal having a disabled state, and the buffer chip swaps signals received via the second buffer pads to generate first swapped signals, and respectively communicates the first swapped signals to the first buffer pads in response to the swap enable signal having an enabled state.
Abstract:
An operating method of a memory controller configured to control a memory device including memory blocks each for storing a plurality of pages is provided. The operating method includes transferring a program command to the memory device based on a write request from a host, updating a valid page bitmap representing validity of a plurality of pages based on valid page information received from the memory device, calculating a fragmentation ratio representing a segmentation degree between at least one valid page and at least one invalid page of a memory block based on the valid page bitmap, determining source blocks among the memory blocks in ascending order of fragmentation ratios, and performing garbage collection on the source blocks.
Abstract:
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as long-term evolution (LTE). A phase shifter device according to various embodiments of the present disclosure may include: a first board configured to comprise a phase changing rail; and a second board configured to comprise an input rail connected to an input port, a first output rail connected to a first output port, a second output rail connected to a second output port, and a connection rail connecting the first output rail with the second output rail. The first board may be disposed to be spaced a predetermined distance apart from the second board so as to face and overlay the second board. The phase of a signal passing through a first section of the connection rail may vary by a first value depending on the rotation of the first board. The signal may be divided into a first signal transmitted to the first output port and a second signal transmitted to the second output port.
Abstract:
An electronic device and battery included therein are disclosed. The device includes a battery which itself comprises a jelly-roll structure having a rolled stack of a cathode, a separator, and an anode; an outer cover layer enclosing surfaces of the jelly-roll; and a pouch sealing the jelly-roll and the outer cover layer. The jelly-roll includes a first surface, a second surface disposed in a opposite direction, a third surface corresponding to one side of the rolled stack and connecting the first surface and the second surface, and a fourth surface corresponding to other side of the rolled stack, connecting the first surface and the second surface, and disposed in a direction opposite to the third surface. The outer cover layer includes a first portion, a second portion, a third portion, and a fourth portion bonded to first, second, third and fourth surfaces, respectively.
Abstract:
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). According to embodiments in the present disclosure, an antenna device for dual polarization of a wireless communication system, comprises a print circuit board (PCB); a first feeding line configured to provide a first polarization signal; a second feeding configured to provide a second polarization signal; and a patch antenna comprising a radiating region and cutting regions. Objects corresponding to the cutting regions are disposed to support the radiating region on the PCB.
Abstract:
A cooling system for semiconductor equipment includes a chamber, an electrostatic chuck in the chamber, a coolant pipe housing in at least one of the chamber and the electrostatic chuck, the coolant pipe housing having an internal space, a coolant pipe at least partially in the internal space of the coolant pipe housing, and a flow controller configured to control a flow velocity of the coolant flowing along the coolant pipe so that the flow velocity periodically reaches a highest speed and a lowest speed.