公开(公告)号：US12288738B2

公开(公告)日：2025-04-29

申请号：US17227850

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Park ,  Jongseob Kim ,  Jaejoon Oh ,  Soogine Chong ,  Sunkyu Hwang

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L29/20

Abstract: Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

公开(公告)号：US12218233B2

公开(公告)日：2025-02-04

申请号：US17902383

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejoon Oh ,  Jongseob Kim

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

Abstract: A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

公开(公告)号：US11888059B2

公开(公告)日：2024-01-30

申请号：US17349327

申请日：2021-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun Hwang ,  Jongseob Kim ,  Joonyong Kim ,  Younghwan Park ,  Junhyuk Park ,  Dongchul Shin ,  Jaejoon Oh ,  Soogine Chong ,  Sunkyu Hwang

IPC: H01L29/10 ,  H01L29/778 ,  H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7803 ,  H01L29/7831

Abstract: Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

公开(公告)号：US11069802B2

公开(公告)日：2021-07-20

申请号：US16703128

申请日：2019-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun Hwang ,  Jongseob Kim ,  Joonyong Kim ,  Younghwan Park ,  Junhyuk Park ,  Dongchul Shin ,  Jaejoon Oh ,  Soogine Chong ,  Sunkyu Hwang

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

Abstract: Provided is a field effect transistor (FET) including a gradually varying composition channel. The FET includes: a drain region; a drift region on the drain region; a channel region on the drift region; a source region on the channel region; a gate penetrating the channel region and the source region in a vertical direction; and a gate oxide surrounding the gate. The channel region has a gradually varying composition along the vertical direction such that an intensity of a polarization in the channel region gradually varies.

公开(公告)号：US12278281B2

公开(公告)日：2025-04-15

申请号：US17475700

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Hwang ,  Jaejoon Oh ,  Jongseob Kim

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47

Abstract: A high electron mobility transistor (HEMT) includes an active region, in which a channel is formed, and a field region surrounding the active region. The HEMT may include a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a source and a drain on the barrier layer in the active region; and a gate on the barrier layer. The gate may protrude from the active region to the field region on the barrier layer. The gate may include a first gate and a second gate. The first gate may be in the active region and the second gate may be in the boundary region between the active region and the field region. A work function of the second gate may be different from a work function of the first gate.

公开(公告)号：US12218206B2

公开(公告)日：2025-02-04

申请号：US17685886

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Hwang ,  Jongseob Kim

IPC: H01L29/08 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A method of manufacturing a power semiconductor device includes forming a channel separation pattern on a substrate; forming a passivation layer on the substrate and the channel separation pattern; forming a gate hole, a source hole, and a drain hole penetrating the passivation layer in a same process step; and simultaneously forming a gate electrode pattern, a source electrode pattern, and a drain electrode pattern. The gate electrode pattern may be formed on the channel separation pattern. A side surface of the gate electrode pattern and a side surface of the channel separation pattern may have a step difference.

公开(公告)号：US12119397B2

公开(公告)日：2024-10-15

申请号：US17465212

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Hwang ,  Jongseob Kim ,  Joonyong Kim ,  Younghwan Park ,  Junhyuk Park ,  Jaejoon Oh ,  Injun Hwang

IPC: H01L29/00 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66431

Abstract: A semiconductor integrated circuit device includes: a channel layer, a barrier layer; a first p-type semiconductor layer and a second p-type semiconductor layer, spaced apart from each other on the barrier layer; and a passivation layer on the first p-type semiconductor layer and the second p-type semiconductor layer. The passivation layer may partially inactivate a dopant of at least one of the first p-type semiconductor layer and the second p-type semiconductor layer.

公开(公告)号：US12040391B2

公开(公告)日：2024-07-16

申请号：US17398407

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyong Kim ,  Sunkyu Hwang ,  Jongseob Kim ,  Junhyuk Park

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66462

Abstract: Provided are a power device and a method of manufacturing the same. The power device may include a channel layer; a source and a drain at respective sides of the channel layer; a gate on the channel layer between the source and the drain; a passivation layer covering the source, the drain, and the gate; and a plurality of field plates in the passivation layer. The plurality of field plates may have different thicknesses. The plurality of field plates may have different widths, different pattern shapes, or both different widths and different pattern shapes.

公开(公告)号：US12002879B2

公开(公告)日：2024-06-04

申请号：US17098896

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Hwang ,  Joonyong Kim ,  Jongseob Kim ,  Junhyuk Park ,  Boram Kim ,  Younghwan Park ,  Dongchul Shin ,  Jaejoon Oh ,  Soogine Chong ,  Injun Hwang

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/66462 ,  H01L29/7787

Abstract: Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

公开(公告)号：US11837642B2

公开(公告)日：2023-12-05

申请号：US17016877

申请日：2020-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soogine Chong ,  Jongseob Kim ,  Joonyong Kim ,  Younghwan Park ,  Junhyuk Park ,  Dongchul Shin ,  Jaejoon Oh ,  Sunkyu Hwang ,  Injun Hwang

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L21/765 ,  H01L23/31 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42316 ,  H01L21/022 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/28587 ,  H01L21/765 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a channel layer including a channel; a channel supply layer on the channel layer; a channel separation pattern on the channel supply layer; a gate electrode pattern on the channel separation pattern; and an electric-field relaxation pattern protruding from a first lateral surface of the gate electrode pattern in a first direction parallel with an upper surface of the channel layer. An interface between the channel layer and the channel supply layer is adjacent to channel. A size of the gate electrode pattern in the first direction is different from a size of the channel separation pattern in the first direction. The gate electrode pattern and the electric-field relaxation pattern form a single structure.