公开(公告)号：US20240363552A1

公开(公告)日：2024-10-31

申请号：US18768684

申请日：2024-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulsoon CHANG ,  Sangki KIM ,  Ilgeun JUNG ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/76877

Abstract: A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.

公开(公告)号：US20240274664A1

公开(公告)日：2024-08-15

申请号：US18409269

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin JU ,  Chansic YOON ,  Gyuhyun KIL ,  Junghoon HAN ,  Weonhong KIM

IPC: H01L29/08 ,  H10B12/00

CPC classification number: H01L29/0847 ,  H10B12/50

Abstract: An integrated circuit device includes a gate stack on a substrate, a spacer on first and second sidewalls of the gate stack, a source/drain area in an upper portion of the substrate on first and second sides of the gate stack, a cover semiconductor layer on the source/drain area, an interlayer insulating film on the cover semiconductor layer and surrounding sidewalls of the gate stack, and a contact in a contact hole that penetrates the interlayer insulating film and the cover semiconductor layer, the contact having a bottom portion contacting the cover semiconductor layer and the source/drain area.

公开(公告)号：US20210375759A1

公开(公告)日：2021-12-02

申请号：US17398043

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik LEE ,  Joongwon SHIN ,  Jihoon CHANG ,  Junghoon HAN ,  Junwoo LEE

IPC: H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

公开(公告)号：US20210104462A1

公开(公告)日：2021-04-08

申请号：US16885438

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juik LEE ,  Joongwon SHIN ,  Jihoon CHANG ,  Junghoon HAN ,  Junwoo LEE

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H01L23/522 ,  H01L27/108 ,  H01L23/00

Abstract: A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug.

公开(公告)号：US20210175133A1

公开(公告)日：2021-06-10

申请号：US16898943

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Junyong NOH ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L21/66 ,  H01L21/78

Abstract: A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall.

公开(公告)号：US20230154876A1

公开(公告)日：2023-05-18

申请号：US18093880

申请日：2023-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L21/561 ,  H01L24/13 ,  H01L24/96 ,  H01L24/73 ,  H01L2224/81801 ,  H01L2924/1304 ,  H01L2924/18162 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/12105

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US20220262743A1

公开(公告)日：2022-08-18

申请号：US17391659

申请日：2021-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulsoon CHANG ,  Sangki KIM ,  Ilgeun JUNG ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/768

Abstract: A semiconductor device may include a semiconductor substrate, a crack-blocking layer and a crack-blocking portion. The semiconductor substrate may include a plurality of chip regions and a scribe lane region configured to surround each of the plurality of the chip regions. A trench may be defined by one or more inner surfaces of the semiconductor device to be formed in the scribe lane region. The crack-blocking layer may be on an inner surface of the trench. The crack-blocking layer may be configured to block a spreading of a crack, which is generated in the scribe lane region during a cutting of the semiconductor substrate along the scribe lane region, from spreading into any of the chip regions. The crack-blocking portion may at least partially fill the trench and may be configured to block the spreading of the crack from the scribe lane region into any of the chip regions.

公开(公告)号：US20220084885A1

公开(公告)日：2022-03-17

申请号：US17201457

申请日：2021-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon HAN ,  Juik LEE

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/31

Abstract: A semiconductor device includes a substrate, an interlayer insulating layer covering an upper surface of the substrate, an individual device in the interlayer insulating layer, a lower insulating layer covering a lower surface of the substrate, a through-silicon-via (TSV) structure extending through the substrate, the interlayer insulating layer and the lower insulating layer, a conductive pad connected to an upper end of the TSV structure, a via insulating layer surrounding the TSV structure, a capping insulating layer surrounding the TSV structure outside the via insulating layer. The via insulating layer and the capping insulating layer have an air gap therebetween. A portion of the air gap extends into the lower insulating layer.

公开(公告)号：US20210043591A1

公开(公告)日：2021-02-11

申请号：US16795658

申请日：2020-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung CHOI ,  Sooho SHIN ,  Yeonjin LEE ,  Junghoon HAN

IPC: H01L23/00 ,  H01L21/56

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

公开(公告)号：US20170294440A1

公开(公告)日：2017-10-12

申请号：US15631105

申请日：2017-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Sohyun PARK ,  Bong-Soo KIM ,  Yoosang HWANG ,  Dong-Wan KIM ,  Junghoon HAN

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L21/0274 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/565 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10897 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/60

Abstract: A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask layer on the supporter layer, forming a first edge blocking layer on the mask layer, forming a mask pattern by etching the mask layer, forming a hole, forming a lower electrode in the hole, forming a supporter mask layer on the supporter layer, forming a second edge blocking layer on the supporter mask layer, forming a supporter mask pattern by patterning the supporter mask layer, forming a supporter opening passing through the supporter layer, removing the molding layer, forming a capacitor dielectric layer and an upper electrode on the lower electrode, forming an interlayer insulating layer on the upper electrode, and planarizing the interlayer insulating layer. The hole passes through the supporter layer, the molding layer and the etch stop layer.