公开(公告)号：US10304834B2

公开(公告)日：2019-05-28

申请号：US15939914

申请日：2018-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Jungtaek Kim ,  Yihwan Kim ,  Woo Bin Song ,  Dongsuk Shin ,  Seung Ryul Lee

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/84 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/12

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; an active pattern spaced apart from the substrate and extending in a first direction; and a gate structure on the active pattern and extending in a second direction crossing the first direction, wherein a lower portion of the active pattern extends in the first direction and includes a first lower surface that is sloped with respect to an upper surface of the substrate.

公开(公告)号：US20240136425A1

公开(公告)日：2024-04-25

申请号：US18190837

申请日：2023-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edwardnamkyu Cho ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Sumin Yu ,  Seojin Jeong

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.

公开(公告)号：US20240128321A1

公开(公告)日：2024-04-18

申请号：US18378874

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongryeol Yoo ,  Jungtaek Kim

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes an active region including a first portion and a second portion; an isolation region on a side surface of the active region; a plurality of active layers stacked and spaced apart from each other in a vertical direction on the first portion of the active region; an epitaxial structure disposed on the second portion of the active region, connected to the plurality of active layers, and overlapping the isolation region in the vertical direction; a gate structure extending by intersecting the active region and surrounding each of the plurality of active layers; and a gate spacer on a side surface of the gate structure. The epitaxial structure includes a blocking layer and a source/drain structure on the blocking layer. The blocking layer includes a plurality of active blocking portions contacting the plurality of active layers, respectively, and at least one first bent portion bent and extending from at least one of the plurality of active blocking portions and contacting the gate spacer.

公开(公告)号：US11888026B2

公开(公告)日：2024-01-30

申请号：US17467944

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US20220085202A1

公开(公告)日：2022-03-17

申请号：US17533499

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngdae Cho ,  Sunguk Jang ,  Sujin Jung ,  Jungtaek Kim ,  Sihyung Lee

IPC: H01L29/78 ,  H01L29/423

Abstract: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.

公开(公告)号：US11183562B2

公开(公告)日：2021-11-23

申请号：US16750273

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Yi ,  Moonseung Yang ,  Jungtaek Kim

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/417 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/265

Abstract: A semiconductor device includes a substrate including an active region in a first direction, a plurality of channel layers on the active region and disposed in a direction perpendicular to an upper surface of the substrate, a gate electrode respectively surrounding the plurality of channel layers, and a source/drain structure respectively disposed on both sides of the gate electrode in the first direction and connected to each of the plurality of channel layers. The gate electrode extends in a second direction crossing the first direction. The gate electrode includes an overlapped portion in a region of the gate electrode on an uppermost channel layer of the plurality of channel layers. The overlapped portion of the gate electrode overlaps the source/drain structure in the first direction and has a side surface inclined toward the upper surface of the substrate.

公开(公告)号：US20240234541A9

公开(公告)日：2024-07-11

申请号：US18190837

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Edwardnamkyu Cho ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Sumin Yu ,  Seojin Jeong

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A manufacturing method of a semiconductor device, includes forming a plurality of main gate sacrificial patterns spaced apart from each other on a stacked structure of subgate sacrificial patterns and semiconductor patterns; forming a first insulating layer between main gate sacrificial patterns; removing the main gate sacrificial patterns; removing the subgate sacrificial patterns; forming a main gate dummy pattern in a space from which the main gate sacrificial patterns are removed; forming a plurality of subgate dummy patterns in a space from which the subgate sacrificial patterns are removed; forming a recess under a space where the first insulating layer is removed; forming a source/drain pattern within the recess; forming a second insulating layer on the source/drain pattern; removing the main gate dummy pattern and the subgate dummy patterns; and forming a gate electrode in a space where the main gate dummy pattern and the subgate dummy patterns are removed.

公开(公告)号：US20240096945A1

公开(公告)日：2024-03-21

申请号：US18527453

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US20240030286A1

公开(公告)日：2024-01-25

申请号：US18140905

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Heo ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Edward Namkyu Cho ,  Ryong Ha

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: An integrated circuit device includes a plurality of fin-type active areas extending in a first horizontal direction on a substrate, a plurality of channel regions respectively on the plurality of fin-type active areas, a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction, and a plurality of source/drain regions respectively at positions adjacent to the plurality of gate lines on the plurality of fin-type active areas and respectively in contact with the plurality of channel regions, and the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein.

公开(公告)号：US11862682B2

公开(公告)日：2024-01-02

申请号：US17511778

申请日：2021-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Yi ,  Moonseung Yang ,  Jungtaek Kim

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/265

CPC classification number: H01L29/1037 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/30604 ,  H01L21/31116 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate including an active region in a first direction, a plurality of channel layers on the active region and disposed in a direction perpendicular to an upper surface of the substrate, a gate electrode respectively surrounding the plurality of channel layers, and a source/drain structure respectively disposed on both sides of the gate electrode in the first direction and connected to each of the plurality of channel layers. The gate electrode extends in a second direction crossing the first direction. The gate electrode includes an overlapped portion in a region of the gate electrode on an uppermost channel layer of the plurality of channel layers. The overlapped portion of the gate electrode overlaps the source/drain structure in the first direction and has a side surface inclined toward the upper surface of the substrate.