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    Programming methods for three-dimensional memory devices having multi-bit programming, and three-dimensional memory devices programmed thereby
    14.
    发明授权
    Programming methods for three-dimensional memory devices having multi-bit programming, and three-dimensional memory devices programmed thereby 有权
    具有多位编程的三维存储器件的编程方法以及由此编程的三维存储器件

    公开(公告)号：US08767473B2

    公开(公告)日：2014-07-01

    申请号：US13962451

    申请日：2013-08-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunil Shim ,  Sunghoi Hur ,  Kihyun Kim ,  Hansoo Kim ,  Jaehun Jeong

    IPC: G11C16/00

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3427

    Abstract: In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states.

    Abstract translation: 在具有相对于衬底在水平和垂直方向上延伸的存储器单元阵列的三维存储器件的多位编程的方法中，该方法包括首先将要编程的存储器单元编程为第一组 状态。 然后，首先对与第一组状态中的一个相邻的要存储单元相邻的至少一个相邻存储单元进行编程。 在对所述至少一个相邻存储器单元进行第一编程之后，将要编程的存储器单元的第二编程为第二组状态之一，其中所述第二组状态具有大于所述状态数 第一套状态。

    MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
    15.
    发明申请
    MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE 审中-公开
    半导体存储器件的制造方法

    公开(公告)号：US20140033143A1

    公开(公告)日：2014-01-30

    申请号：US13861720

    申请日：2013-04-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kihyun Kim

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  H01J37/3026 ,  H01J37/3174 ,  H01J2237/31764

    Abstract: A method of manufacturing a semiconductor device is provided which includes forming a target layout; producing a skewed layout that includes retargeting the target layout; detecting an envelope of the skewed layout; generating a jog-free layout according to the detected envelope; fragmenting the jog-free layout; acquiring a layout that converges towards the skewed layout by performing an optical proximity correction on the fragmented jog-free layout; and patterning a material for forming the semiconductor device using the acquired layout.

    Abstract translation: 提供一种制造半导体器件的方法，其包括形成目标布局; 产生倾斜的布局，包括重新定位目标布局; 检测倾斜布局的包络; 根据检测到的信封产生无点击布局; 破碎无轨布局; 通过对分散的无点击布局进行光学邻近校正来获取收敛于偏斜布局的布局; 以及使用获取的布局图案化用于形成半导体器件的材料。

    Semiconductor device and data storage system including the same
    17.
    发明授权
    Semiconductor device and data storage system including the same 有权

    公开(公告)号：US12230573B2

    公开(公告)日：2025-02-18

    申请号：US17713559

    申请日：2022-04-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seyong Oh ,  Kihyun Kim ,  Jihwan You

    IPC: H01L23/535 ,  H10B43/27 ,  H10B43/40

    Abstract: A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a lower structure including a semiconductor substrate, a circuit element on the semiconductor substrate, a circuit interconnection structure on the semiconductor substrate, the circuit interconnection structure including a plurality of connection patterns on different levels and electrically connected to the circuit element, and a lower insulating structure covering the circuit element and the circuit interconnection structure; and an upper structure including an upper substrate in contact with an upper surface of the lower insulating structure, a stack structure on the upper substrate, the stack structure including interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, and a vertical memory structure penetrating through the stack structure in the vertical direction.

    IMAGE DENOISING METHOD
    18.
    发明公开
    IMAGE DENOISING METHOD 审中-公开

    公开(公告)号：US20240320805A1

    公开(公告)日：2024-09-26

    申请号：US18612094

    申请日：2024-03-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Nohong Kwak ,  Donyun Kim ,  Jiwon Kang ,  Kihyun Kim

    IPC: G06T5/70 ,  G06T7/00 ,  G06V10/44

    CPC classification number: G06T5/70 ,  G06T7/0004 ,  G06V10/44 ,  G06T2207/20081 ,  G06T2207/30148

    Abstract: There is provided an image denoising method including extracting a noise patch from a noisy image, outputting a noise parameter by inputting the noise patch to a noise parameter estimation network (NPE-net), generating imitated virtual noise based on the output noise parameter, generating a noisier image by adding the imitated virtual noise to the noisy image, training a denoise deep learning model by inputting the noisy image and the noisier image as a pair to the denoise deep learning model, inputting the noisy image to the trained denoise deep learning model, and outputting a denoise image obtained by removing noise from the noisy image by the trained denoise deep learning model.

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