公开(公告)号：US20220093631A1

公开(公告)日：2022-03-24

申请号：US17352862

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Shinhwan KANG ,  Jeehoon HAN

IPC: H01L27/11575 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11548 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor device includes a substrate; a stack structure on the substrate and including an alternating stack of interlayer insulating layers and gate electrodes; first and second separation regions each extending through the stack structure and extending in a first direction; a first upper separation region between the first and second separation regions and extending through a portion of the stack structure; a plurality of channel structures between the first and second separation regions and extending through the stack structure; and a plurality of first vertical structures each extending through a particular one of the first and second separation regions. Each of the first and second separation regions has a first width in a second direction that is perpendicular to the first direction. Each first vertical structure has a second width in the second direction, the second width being greater than the first width.

公开(公告)号：US20210375924A1

公开(公告)日：2021-12-02

申请号：US17400224

申请日：2021-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Seogoo KANG ,  Shinhwan KANG

IPC: H01L27/11582 ,  H01L29/417

Abstract: A semiconductor memory device including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers, gate electrodes arranged on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer, and channel structures penetrating the first, second and third semiconductor layers and the gate electrodes, each respective channel structure of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, and the charge storage film including an upper cover protruding toward the outside of the respective channel structure.

公开(公告)号：US20210359200A1

公开(公告)日：2021-11-18

申请号：US17110524

申请日：2020-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Kohji KANAMORI ,  Unghwan PI ,  Hyuncheol KIM ,  Sungwon YOO ,  Jaeho HONG

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  H01L43/02 ,  G11C11/16 ,  H01L23/522

Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.

公开(公告)号：US20210313344A1

公开(公告)日：2021-10-07

申请号：US17101401

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Joon RYU ,  Young Hwan SON ,  Seo-Goo KANG ,  Jung Hoon JUN ,  Kohji KANAMORI ,  Jee Hoon HAN

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

公开(公告)号：US20190355744A1

公开(公告)日：2019-11-21

申请号：US16526139

申请日：2019-07-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-soo KIM ,  Yong-seok KIM ,  Tae-hun KIM ,  Min-kyung BAE ,  Jae-hoon JANG ,  Kohji KANAMORI

IPC: H01L27/11582 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

公开(公告)号：US20230292515A1

公开(公告)日：2023-09-14

申请号：US18321080

申请日：2023-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Hwan SON ,  Kohji KANAMORI ,  Shin-Hwan KANG ,  Young Jin KWON

IPC: H10B43/27 ,  H01L23/535 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/535 ,  H10B43/40

Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.

公开(公告)号：US20230061301A1

公开(公告)日：2023-03-02

申请号：US17857273

申请日：2022-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdong KIM ,  Seogoo KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/528

Abstract: A semiconductor device includes an upper structure on a lower structure. The upper structure includes a stack structure including gate layers, a vertical memory structure penetrating the stack structure, a bit line electrically connected to the vertical memory structure and below the stack structure, and a conductive pattern electrically connected to the vertical memory structure and on the stack structure. The vertical memory structure includes an insulating core region, a first pad pattern electrically connected to the conductive pattern on the insulating core region, a dielectric structure on a side surface of the insulating core region and a side surface of the first pad pattern, and a channel layer. The channel layer includes a first portion contacting the dielectric structure and a second portion extending from the first portion and between a lower surface of the first pad pattern and an upper surface of the insulating core region.

公开(公告)号：US20230054445A1

公开(公告)日：2023-02-23

申请号：US17739845

申请日：2022-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji KANAMORI ,  Seungyoon KIM ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device includes a stack structure of alternating interlayer insulating layers and gate electrodes, a separation structure vertically penetrating the stack structure and extending in a first direction, to separate the gate electrodes in a second direction, and vertical structures vertically penetrating the stack structure and arranged at a constant pitch. The vertical structures are arranged along array lines sequentially arranged in the second direction away from a side of the separation structure in a plan view. The vertical structures include a channel structure including a channel layer, a contact structure including a metal plug having an upper surface on a level higher than that of an upper surface of the channel structure, and a dummy structure disposed adjacent to the contact structure. The channel structure, the dummy structure, and the contact structure are disposed to be aligned with each other on at least one of the array lines.

公开(公告)号：US20210384210A1

公开(公告)日：2021-12-09

申请号：US17155225

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyoun JO ,  Kohji KANAMORI ,  Kwangyoung JUNG ,  Jeehoon HAN

IPC: H01L27/11556 ,  H01L23/528 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519

Abstract: A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

公开(公告)号：US20210035987A1

公开(公告)日：2021-02-04

申请号：US16844234

申请日：2020-04-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin LEE ,  Jongwon KIM ,  Shinhwan KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11521 ,  H01L27/11556

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.