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公开(公告)号：US10474600B2
公开(公告)日：2019-11-12
申请号：US15825047
申请日：2017-11-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Hongzhong Zheng
Abstract: An apparatus may include a heterogeneous computing environment that may be controlled, at least in part, by a task scheduler in which the heterogeneous computing environment may include a processing unit having fixed logical circuits configured to execute instructions; a reprogrammable processing unit having reprogrammable logical circuits configured to execute instructions that include instructions to control processing-in-memory functionality; and a stack of high-bandwidth memory dies in which each may be configured to store data and to provide processing-in-memory functionality controllable by the reprogrammable processing unit such that the reprogrammable processing unit is at least partially stacked with the high-bandwidth memory dies. The task scheduler may be configured to schedule computational tasks between the processing unit, and the reprogrammable processing unit.
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公开(公告)号：US20190212980A1
公开(公告)日：2019-07-11
申请号：US15916196
申请日：2018-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Peng Gu , Hongzhong Zheng , Robert Brennan
Abstract: A computing accelerator using a lookup table. The accelerator may accelerate floating point multiplications by retrieving the fraction portion of the product of two floating-point operands from a lookup table, or by retrieving the product of two floating-point operands of two floating-point operands from a lookup table, or it may retrieve dot products of floating point vectors from a lookup table. The accelerator may be implemented in a three-dimensional memory assembly. It may use approximation, the symmetry of a multiplication lookup table, and zero-skipping to improve performance.
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公开(公告)号：US20180121120A1
公开(公告)日：2018-05-03
申请号：US15595887
申请日：2017-05-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dimin Niu , Shuangchen Li , Bob Brennan , Krishna T. Malladi , Hongzhong Zheng
IPC: G06F3/06 , G11C11/4096
CPC classification number: G06F3/0631 , G06F3/0604 , G06F3/067 , G06F15/7821 , G11C11/4096
Abstract: A processor includes a plurality of memory units, each of the memory units including a plurality of memory cells, wherein each of the memory units is configurable to operate as memory, as a computation unit, or as a hybrid memory-computation unit.
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公开(公告)号：US09503095B2
公开(公告)日：2016-11-22
申请号：US14838348
申请日：2015-08-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Mingyu Gao , Hongzhong Zheng , Krishna T. Malladi
IPC: H03K19/177 , H01L25/18 , H01L25/00
CPC classification number: H03K19/1776 , H01L25/18 , H01L25/50 , H01L2924/0002 , H03K19/17728 , H03K19/17736 , H01L2924/00
Abstract: According to one general aspect, an apparatus may include a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may include memory cells configured to simultaneously store a plurality of look-up tables, wherein each look-up table is associated with a respective logic function. The reconfigurable look-up table may include a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The reconfigurable look-up table may be configured to perform one logic function at a time, and wherein the logic function is dynamically selected. The plurality of look up tables stored in the memory cells may be configured to be dynamically altered via a write operation to the random access memory array.
Abstract translation: 根据一个一般方面，装置可以包括随机存取存储器阵列，其又包括可重新配置的查找表。 可重构查找表可以包括被配置为同时存储多个查找表的存储器单元，其中每个查找表与相应的逻辑功能相关联。 可重构查找表可以包括配置成基于一组输入信号来激活一行或多行存储器单元的本地行解码器。 可重构查找表可以被配置为一次执行一个逻辑功能，并且其中逻辑功能被动态地选择。 存储在存储器单元中的多个查找表可以被配置为通过写入操作来动态地改变到随机存取存储器阵列。
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公开(公告)号：US20240329872A1
公开(公告)日：2024-10-03
申请号：US18744351
申请日：2024-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673
Abstract: A method for in-memory computing. In some embodiments, the method includes: executing, by a first function-in-memory circuit, a first instruction, to produce, as a result, a first value, wherein a first computing task includes a second computing task and a third computing task, the second computing task including the first instruction; storing, by the first function-in-memory circuit, the first value in a first buffer; reading, by a second function-in-memory circuit, the first value from the first buffer; and executing, by a second function-in-memory circuit, a second instruction, the second instruction using the first value as an argument, the third computing task including the second instruction, wherein: the storing, by the first function-in-memory circuit, of the first value in the first buffer includes directly storing the first value in the first buffer.
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Patent Agency Ranking
公开(公告)号：US11947961B2
公开(公告)日：2024-04-02
申请号：US18060276
申请日：2022-11-30
Applicant: Samsung Electronics Co. Ltd.
Inventor： Peng Gu , Krishna T. Malladi , Hongzhong Zheng
CPC classification number: G06F9/3001 , G06F7/00 , G06F7/4876 , G06F9/3004 , G06F12/0207 , G06F17/16 , G06F2212/1024
Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.
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公开(公告)号：US11921638B2
公开(公告)日：2024-03-05
申请号：US17833219
申请日：2022-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Hongzhong Zheng
IPC: G06F12/08 , G06F12/0866 , G06F12/12 , G06F12/0868 , G06F12/0897
CPC classification number: G06F12/0866 , G06F12/0868 , G06F12/0897 , G06F12/12 , G06F2212/1041 , G06F2212/225 , G06F2212/283
Abstract: According to some embodiments of the present invention, there is provided a hybrid cache memory for a processing device having a host processor, the hybrid cache memory comprising: a high bandwidth memory (HBM) configured to store host data; a non-volatile memory (NVM) physically integrated with the HBM in a same package and configured to store a copy of the host data at the HBM; and a cache controller configured to be in bi-directional communication with the host processor, and to manage data transfer between the HBM and NVM and, in response to a command received from the host processor, to manage data transfer between the hybrid cache memory and the host processor.
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公开(公告)号：US20240004646A1
公开(公告)日：2024-01-04
申请号：US18368515
申请日：2023-09-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Wenqin Huangfu
CPC classification number: G06F9/3001 , G06F9/30036 , G06F7/57 , G06F9/30098 , G06F7/5318 , G06F9/3016
Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.
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公开(公告)号：US11853210B2
公开(公告)日：2023-12-26
申请号：US17246448
申请日：2021-04-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Krishna T. Malladi , Andrew Chang , Ehsan Najafabadi
CPC classification number: G06F12/0646 , G06F9/30047 , G06F9/44505 , G06F12/0891 , G06F13/1668 , G06F13/4234
Abstract: Provided are systems, methods, and apparatuses for providing a storage resource. The method can include: operating a first controller coupled to a network interface in accordance with a cache coherent protocol; performing at least one operation on data associated with a cache using a second controller coupled to the first controller and coupled to a first memory; and storing the data on a second memory coupled to one of the first controller or the second controller.
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公开(公告)号：US20230101422A1
公开(公告)日：2023-03-30
申请号：US18060276
申请日：2022-11-30
Applicant: Samsung Electronics Co. Ltd.
Inventor： Peng Gu , Krishna T. Malladi , Hongzhong Zheng
Abstract: According to some example embodiments of the present disclosure, in a method for a memory lookup mechanism in a high-bandwidth memory system, the method includes: using a memory die to conduct a multiplication operation using a lookup table (LUT) methodology by accessing a LUT, which includes floating point operation results, stored on the memory die; sending, by the memory die, a result of the multiplication operation to a logic die including a processor and a buffer; and conducting, by the logic die, a matrix multiplication operation using computation units.
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